Gather using index array and finite state machine

Patent metadata

Field	Value
Publication number	US-2017192934-A1
Application number	US-201514616323-A
Country	US
Kind code	A1
Filing date	Feb 6, 2015
Priority date	Jun 2, 2012
Publication date	Jul 6, 2017
Grant date	—

Abstract

Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

First claim

What is claimed is:

1 . A computer implemented method comprising:
copying, from one or more registers, a set of indices and a corresponding set of mask elements to an index array; generating a set of addresses from the set of indices in the index array for at least each corresponding mask element having a first value; accessing an address from the set of addresses to load a corresponding data element if a corresponding mask element has said first value; writing the corresponding data element at an in-register position in a destination vector register according to a respective in-register position an index, from the set of indices, corresponding to the accessed address from the set of addresses; and changing the values of corresponding mask elements from the first value to a second value responsive to completion of their respective loads.

2 . The computer implemented method of claim 1 being performed responsive to a single instruction multiple data (SIMD) gather instruction.

3 . The computer implemented method of claim 2 said copying, the set of indices and the corresponding set of mask elements to said index array being performed responsive to a first micro-operation generated by decoding said SIMD gather instruction.

Assignees

• Intel Corp

Inventors

• Sperber Zeev
• Valentine Robert
• Patkin Guy
• Shwartsman Stanislav
• Raikin Shlomo
• Yanover Igor
• Ofir Gal

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F15/8007 Primary

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title