Electronic device

Patent metadata

Field	Value
Publication number	US-2017192924-A1
Application number	US-201715399402-A
Country	US
Kind code	A1
Filing date	Jan 5, 2017
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

According to one embodiment, an electronic device includes a USB Type-C connector connected to a second electronic device, a processor connected to the USB Type-C connector and including four terminals outputting an image signal, and a USB controller connected to the USB Type-C connector and including two terminals outputting USB 3.x signal. The USB Type-C connector includes two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX1, RX1, TX2 and RX2 defined under the USB Type-C standard. The image signal and the USB 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX1, RX1, TX2 and RX2.

First claim

What is claimed is:

1 . An electronic device, comprising:
a USB Type-C connector connectable to a second electronic device, the connector including two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX 1 , RX 1 , TX 2 and RX 2 defined under the USB Type-C standard; a processor connected to the USB Type-C connector and including four terminals outputting an image signal; and a USB controller connected to the USB Type-C connector and including two terminals outputting USB 3.x signal, wherein the image signal and the USE 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX 1 , RX 1 , TX 2 and RX 2 .

2 . The electronic device of claim 1 , wherein
the image signal is output via the two USB 2.0 pins D and D and two pins of the four USB 3.x pins TX 1 , RX 1 , TX 2 and RX 2 .

3 . The electronic device of claim 2 , wherein
the image signal corresponds to signals of four lanes conforming to DisplayPort standard; the four USB 3.x pins comprise a first pair of pins TX 1 and RX 1 and a second pair of pins TX 2 and RX 2 ; the USB 3.x signal is output via the first pair of pins TX 1 and RX 1 ; DisplayPort signals of lane 0 and lane 1 of lower two lanes are output via the second pair of pins TX 2 and RX 2 ; and DisplayPort signals of lane 2 and lane 3 of upper two lanes are output via the two USB 2.0 pins D and D.

4 . The electronic device of claim 2 , wherein
the image signal corresponds to signals of four lanes conforming to DisplayPort standard; the four USB 3.x pins comprise a first pair of pins TX 1 and RX 1 and a second pair of pins TX 2 and RX 2 ; DisplayPort signals of lane 0 and lane 1 of lower two lanes are output via the first pair of pins TX 1 and RX 1 , and DisplayPort signals of lane 2 and lane 3 of upper two lanes are output via the second pair of pins TX 2 and RX 2 ; and the USB 3.x signal is output via the two USB 2.0 pins D and D.

5 . The electronic device of claim 1 , further comprising:
a determiner which determines a type of the second electronic device, wherein the image signal and the USB 3.x signal are output via the two USB 2.0 pins D and D and the four USB 3.x pins TX 1 , RX 1 , TX 2 , and RX 2 when the determiner determines the type of the second electronic device as a first type, and, the image signal and the USB 3.x signal are output via the four USB 3.x pins TX 1 , RX 1 , TX 2 , and RX 2 or via the four USB 3.x pins TX 1 , RX 1 , TX 2 , and RX 2 when the determiner determines the type of the second electronic device as a second type.

6 . The electronic device of claim 5 , wherein
the image signal corresponds to DisplayPort signals of four lanes; the four USB 3.x pins comprises a first pair of pins TX 1 and RX 1 and a second pair of pins TX 2 and RX 2 , and when the determiner determines the type of the second electronic device as a first type, the USB 3.x signal is output via the first pair of pins TX 1 and RX 1 , DisplayPort signals of lane 0 and lane 1 of lower two lanes are output via the second pair of pins TX 2 and RX 2 , and DisplayPort signals of lane 2 and lane 3 of upper two lanes are output via the two USB 2.0 pins D and D.

7 . The electronic device of claim 5 , wherein
the image signal corresponds to DisplayPort signals of four lanes; the four USB 3.x pins comprise a first pair of pins TX 1 and RX 1 and a second pair of pins TX 2 and RX 2 ; when the determiner determines the type of the second electronic device as a first type, DisplayPort signals of lane 0 and lane 1 of lower two lanes are output via the first pair of pins TX 1 and RX 1 , DisplayPort signals of lane 2 and lane 3 of upper two lanes are output via the second pair of pins TX 2 and RX 2 USB, and the USB 3.x signal is output via the two USB 2.0 pins D and D.

8 . An electronic device, comprising:
four pins for an image signal; two pins for USB 3.x signal; and a USB Type-C connector connectable to another electronic device, wherein the USB Type-C connector includes two USB 2.0 pins D and D defined under USB Type-C standard and four USB 3.x pins TX 1 , RX 1 , TX 2 , and RX 2 defined under the USB Type-C standard; and the four pins for the image signal and the two pins for the USB 3.x signal are connected to the two USB 2.0 pins D and D and the four USB 3.x pins TX 1 , RX 1 , TX 2 , and RX 2 .

9 . The electronic device of claim 8 , wherein
the four pins for the image signal are connected to the two USB 2.0 pins and two pins of the four USB 3.x pins TX 1 , RX 1 , TX 2 , and RX 2 .

10 . The electronic device of claim 9 , wherein
the image signal corresponds to DisplayPort signals of four lanes; the four USB 3.x pins comprise a first pair of pins TX 1 and RX 1 and a second pair of pins TX 2 and RX 2 ; and two pins for DisplayPort signals of lane 2 and lane 3 of upper two lanes of the four lanes, two pins for DisplayPort signals of lane 0 and lane 1 of lower two lanes of the four lanes, and two pins for the USB 3.x signal are connected to the two USB 2.0 pins D and D, the first pair of pins TX 1 and RX 1 , and the second pair of pins TX 2 and RX 2 .

11 . The electronic device of claim 10 , wherein
the two pins for the DisplayPort signals of lane 0 and lane 1 of lower two lanes are connected to one of the first pair of pins TX 1 and RX 1 and the second pair of pins TX 2 and RX 2 ; and the two pins for the DisplayPort signals of lane 2 and lane 3 of upper two lanes are connected to the other of the first pair of pins TX 1 and RX 1 and the second pair of pins TX 2 and RX 2 , and the two USB 2.0 pins D and D.

12 . The electronic device of claim 11 , wherein
the two pins for the DisplayPort signals of lane 0 and lane 1 of lower two lanes are connected to the second pair of pins TX 2 and RX 2 ; the two pins for the DisplayPort signals of lane 2 and lane 3 of upper two lanes are connected to the two USB 2.0 pins D and D; and the two pins for the USB 3.x signal are connected to the first pair of pins TX 1 and RX 1 .

13 . The electronic device of claim 11 , wherein
the two pins for the DisplayPort signals of lane 0 and lane 1 of lower two lanes are connected to the first pair of pins TX 1 and RX 1 ; the two pins for the DisplayPort signals of lane 2 and lane 3 of upper two lanes are connected to the second pair of pins TX 2 and RX 2 ; and the two pins for the USB 3.x signal are connected to the two USB 2.0 pins D and D.

Assignees

• Toshiba Kk
• Toshiba Client Solutions Co Ltd

Inventors

• Chiba Hiroaki

Classifications

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title