Error counters on a memory device

Patent metadata

Field	Value
Publication number	US-2017192843-A1
Application number	US-201415314831-A
Country	US
Kind code	A1
Filing date	Aug 8, 2014
Priority date	Aug 8, 2014
Publication date	Jul 6, 2017
Grant date	—

Abstract

Example implementations relate to tracking memory unit errors on a memory device. In example implementations. a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

First claim

We claim

1 . A memory module comprising:
a repair unit; and a memory device having on-die error-correcting code (ECC), wherein:
the memory device comprises a plurality of memory units and a plurality of error counters;
one of the plurality of error counters is to count errors, detected by the on-die ECC, in a first memory unit of the plurality of memory units;
a post package repair (PPR) is initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value; and
during the PPR, data in the first memory unit is copied to the repair unit.

2 . The memory module of claim 1 , wherein each of the plurality of error counters is associated with a respective one of the plurality of memory units.

3 . The memory module of claim 1 , further comprising a register associated with the one of the plurality of error counters, wherein:
the first memory unit comprises a first plurality of memory elements; and the register is to store a first memory address that is common to the first plurality of memory elements.

4 . The memory module of claim 3 , wherein in response to a determination that the on-die ECC has not detected errors in the first memory unit for a predetermined length of time:
the one of the plurality of error counters is to count errors, detected by the on-die ECC, in a second memory unit of the plurality of memory units, the second memory unit comprising a second plurality of memory elements; and the register is to store a second memory address that is common to the second plurality of memory elements.

5 . The memory module of claim 1 , wherein:
any of the plurality of error counters is capable of counting errors, detected by the on-die ECC, in any of the plurality of memory units; and the plurality of error counters are assigned to respective ones of the plurality of memory units in a first-in, first-out (FIFO) manner.

6 . A machine-readable storage medium encoded with instructions executable by a processor, the machine-readable storage medium comprising:
instructions to determine whether a value of one of a plurality of error counters on a memory device equals a threshold value, wherein:
the memory device comprises on-die error-correcting code (ECC);
the one of the plurality of error counters is associated with a memory unit on the memory device; and
the one of the plurality of error counters is to be incremented in response to an error being detected, by the on-die ECC, in the memory unit; and
instructions to initiate, in response to a determination that the value of the one of the plurality of error counters equals the threshold value, a post package repair (PPR), wherein the PPR comprises replacing the memory unit with a repair unit.

7 . The machine-readable storage medium of claim 6 , further comprising:
instructions to suspend functionality of the on-die ECC during the PPR; instructions to copy, during the PPR, data in the memory unit to a buffer on the memory device; instructions to flush, after the PPR has been completed, data in the buffer to a memory controller, wherein the memory controller is to generate non-erroneous data by correcting erroneous data received from the buffer; instructions to write the non-erroneous data to the repair unit; and instructions to enable, in response to a determination that the write to the repair unit has been completed, functionality of the on-die ECC.

8 . The machine-readable storage medium of claim 6 , further comprising:
instructions to write, during a precharge cycle that is executed in response to a precharge command received, during the PPR, with a read command directed at the memory unit, data to the repair unit instead of writing data back to the memory unit; instructions to use the on-die ECC to correct, during the precharge cycle, errors in the memory unit; and instructions to transmit data, that the on-die ECC is unable to correct, to a memory controller.

9 . The machine-readable storage medium of claim 6 , further comprising instructions to write, in response to a write command that is directed at the memory unit and issued during the PPR, data associated with the write command to the repair unit.

10 . The machine-readable storage medium of claim 6 , further comprising:
instructions to detect, during the PPR, erroneous data that is read from the memory unit; instructions to generate non-erroneous data by correcting the erroneous data; and instructions to write the non-erroneous data to the repair unit.

11 . The machine-readable storage medium of claim 6 , further comprising instructions to receive a PPR status indicator from the memory device, wherein the PPR is initiated if the received PPR status indicator indicates PPR availability on the memory device.

12 . A method comprising:
incrementing, in response to detection of an error in one of a plurality of memory units on a memory device, an error counter on the memory device, wherein:
the error is detected by on-die error-correcting code (ECC) on the memory device; and
the error counter is associated with the one of the plurality of memory units;
performing, in response to a determination that a value of the error counter equals a threshold value, a post package repair (PPR) on the memory device; and copying, during the PPR, data in the one of the plurality of memory units to a repair unit.

13 . The method of claim 12 , wherein the copying comprises writing, during a precharge cycle that is executed in response to a precharge command received, during the PPR, with a read command directed at the one of the plurality of memory units, data to the repair unit instead of writing data back to the one of the plurality of memory units.

14 . The method of claim 13 , further comprising:
using the on-die ECC to correct, during the precharge cycle, errors in the one of the plurality of memory units; and transmitting data, that the on-die ECC is unable to correct, to a memory controller.

15 . The method of claim 12 , further comprising writing, during the PPR, data associated with a write command, that is issued during the PPR and directed to the one of the plurality of memory units, to the repair unit.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Warnes Lidia
• Benedict Melvin K
• Walton Andrew C

Classifications

• G11C29/06 Primary

  Acceleration testing · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title