Cpu system including debug logic for gathering debug information, computing system including the cpu system, and debugging method of the computing system

Patent metadata

Field	Value
Publication number	US-2017192838-A1
Application number	US-201615376222-A
Country	US
Kind code	A1
Filing date	Dec 12, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A central processing unit (CPU) system includes a CPU configured to execute a program based on multiple pieces of register information, a CPU hang-up detector configured to detect a hang-up state of the CPU and generate a CPU hang-up occurrence signal, and a memory that stores debug logic configured to gather the multiple pieces of register information from the CPU in response to the CPU hang-up occurrence signal before a reset operation for the CPU is performed.

First claim

What is claimed is:

1 . A central processing unit (CPU) system, comprising:
a CPU configured to execute a program based on a plurality of pieces of register information; a CPU hang-up detector configured to detect a hang-up state of the CPU and generate a CPU hang-up occurrence signal; and a memory that stores debug logic configured to gather the plurality of pieces of register information from the CPU in response to the CPU hang-up occurrence signal before a reset operation for the CPU is performed.

2 . The CPU system of claim 1 ,
wherein the plurality of pieces of register information comprises first program counter register information including a memory address at which an instruction to be presently executed by the CPU has been stored.

3 . The CPU system of claim 2 ,
wherein when the CPU is configured to execute the program by using a pipe-line method, the plurality of pieces of register information further comprises second program counter register information including a memory address at which an instruction to be presently executed by the CPU has been stored, wherein the second program counter register information is generated on the basis of the first program counter register information and offset information.

4 . The CPU system of claim 1 ,
wherein the plurality of pieces of register information comprises link register information including a memory address at which an instruction to be executed by the CPU in response to a branch return instruction has been stored.

5 . The CPU system of claim 1 ,
wherein the CPU comprises a stack area for storing stack information, wherein the plurality of pieces of register information comprises program state register information indicating an operation state of the CPU and stack pointer register information including a pointer address pointing to the stack information.

6 . The CPU system of claim 1 ,
wherein the debug logic is configured to provide an operation completion signal to the CPU hang-up detector when an operation of gathering the plurality of pieces of register information is completed, wherein the CPU hang-up detector is configured to control performing the reset operation for the CPU in response to the operation completion signal.

7 . The CPU system of claim 6 , further comprising:
a cache unit that stores cache data used when the CPU executes the program, wherein the CPU hang-up detector is configured to control performing the reset operation for the CPU and control performing an operation of preserving the cache data stored in the cache unit.

8 . The CPU system of claim 7 ,
wherein the CPU is configured to flush the preserved cache data to an external memory device and update data stored in the external memory device.

9 . The CPU system of claim 1 ,
wherein the CPU system is a multi-CPU system comprising a plurality of CPUs, wherein the CPU hang-up detector is configured to detect a hang-up state of at least one of the plurality of CPUs and generate the CPU hang-up occurrence signal, wherein the debug logic is configured to gather a plurality of pieces of register information corresponding to each of the plurality of CPUs from the plurality of CPUs in response to the CPU hang-up occurrence signal before a reset operation for the plurality of CPUs is performed.

10 . The CPU system of claim 9 ,
wherein the debug logic comprises a plurality of storage areas respectively storing for each of the plurality of CPUs the plurality of pieces of register information corresponding to each of the plurality of CPUs.

11 . A debugging method of a computing system that includes a central processing unit (CPU) system comprising a CPU configured to execute a program based on a plurality of pieces of register information and a debugger configured to debug the CPU system, the debugging method comprising:
detecting a hang-up state of the CPU system and generating a CPU hang-up occurrence signal; gathering the plurality of pieces of register information from the CPU in response to the CPU hang-up occurrence signal before a reset operation for the CPU system is performed; and debugging, by the debugger, the CPU system based on the gathered plurality of pieces of register information.

12 . The debugging method of claim 11 , further comprising:
controlling the reset operation of the CPU system after completing the gathering of the plurality of pieces of register information.

13 . The debugging method of claim 12 ,
wherein the CPU system further comprises a cache unit configured to store cache data used when the CPU executes the program, and wherein performing the reset operation comprises controlling an operation of preserving the cache data stored in the cache unit.

14 . The debugging method of claim 13 ,
wherein the computing system further comprises a memory device configured to store data used when the CPU executes the program, and wherein the debugging method further comprises flushing the preserved cache data to the memory device and updating data stored in the memory device.

15 . The debugging method of claim 14 ,
wherein the debugging, by the debugger, of the CPU system comprises debugging the CPU system based on updated data stored in the memory device and the gathered plurality of pieces of register information.

16 . A central processing unit (CPU) system, comprising:
a memory that stores debug logic configured to gather a plurality of pieces of register information from a CPU in response to a CPU hang-up occurrence signal before a reset operation for the CPU is performed; and a CPU configured to execute a program based on the plurality of pieces of register information, wherein the central processing unit system is configured to detect a hang-up state of the CPU and generate the CPU hang-up occurrence signal so that the debug logic gathers the plurality of pieces of register information from the CPU in response to the CPU hang-up occurrence signal before a reset operation for the CPU is performed.

17 . The central processing unit system of claim 16 ,
wherein the plurality of pieces of register information comprise a memory address at which an instruction to be presently executed by the CPU has been stored.

18 . The central processing unit system of claim 16 ,
wherein the CPU comprises a stack area for storing stack information, wherein the plurality of pieces of register information comprises program state register information indicating an operation state of the CPU and stack pointer register information including a pointer address pointing to the stack information.

19 . The central processing unit system of claim 16 , further comprising:
a cache unit which stores cache data used when the CPU executes the program, wherein central processing unit system is configured to perform the reset operation for the central processing unit while preserving the cache data stored in the cache unit.

20 . The central processing unit system of claim 19 ,
wherein the central processing unit system is configured to flush the preserved cache data to an external memory device and update data stored in the external memory device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Kyoung-Heon
• Kim Jae-Youl
• Lee Sung-Jae
• Kim Ho-Sung

Classifications

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title