Temporary pipeline marking for processor error workarounds

Patent metadata

Field	Value
Publication number	US-2016266986-A1
Application number	US-201514641553-A
Country	US
Kind code	A1
Filing date	Mar 9, 2015
Priority date	Mar 9, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

First claim

What is claimed is:

1 . A method for temporary pipeline marking for processor error workarounds, the method comprising:
monitoring a pipeline of a processor for an event that is predetermined to: cause a stuck state that results in an errant instruction execution result due to the stuck state or a repeated resource contention causing a performance degradation; marking the pipeline for a workaround action based on detecting the event; triggering a clearing action based on the marking of the pipeline; and clearing the marking of the pipeline based on the triggering of the clearing action.

2 . The method of claim 1 , wherein the pipeline is an execution unit pipeline, the event comprises a pipeline flush event or a rescind event, and the event is associated with a programmable instruction operational code.

3 . The method of claim 2 , wherein the triggering of the clearing action is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code.

4 . The method of claim 3 , wherein finish logic in the processor initiates the clearing action based on the marking and the next instruction having the same instruction type reaching the finish logic.

5 . The method of claim 3 , wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.

6 . The method of claim 1 , wherein the clearing action comprises a complete purging of the pipeline.

7 . The method of claim 1 , wherein the repeated resource contention is with respect to a shared resource and triggering the clearing action further comprises confirming that the event has occurred for a predetermined number of times.

8 . The method of claim 7 , wherein the pipeline is a load store unit pipeline and the event is associated with a memory address.

9 . A computer system for temporary pipeline marking for processor error workarounds, the computer system comprising:
a processor configured to perform a method comprising: monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing a performance degradation; marking the pipeline for a workaround action based on detecting the event; triggering a clearing action based on the marking of the pipeline; and clearing the marking of the pipeline based on the triggering of the clearing action.

10 . The computer system of claim 9 , wherein the pipeline is an execution unit pipeline, the event comprises a pipeline flush event or a rescind event, and the event is associated with a programmable instruction operational code.

11 . The computer system of claim 10 , wherein the triggering of the clearing action is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code.

12 . The computer system of claim 11 , wherein finish logic in the processor initiates the clearing action based on the marking and the next instruction having the same instruction type reaching the finish logic.

13 . The computer system of claim 11 , wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in the stuck state prior to completion of the next instruction.

14 . The computer system of claim 9 , wherein the clearing action comprises a complete purging of the pipeline.

15 . The computer system of claim 9 , wherein the repeated resource contention is with respect to a shared resource and triggering the clearing action further comprises confirming that the event has occurred for a predetermined number of times.

16 . The computer system of claim 15 , wherein the pipeline is a load store unit pipeline and the event is associated with a memory address.

17 . A computer program product for temporary pipeline marking for processor error workarounds, the computer program product comprising:
a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured for: monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing a performance degradation; marking the pipeline for a workaround action based on detecting the event; triggering a clearing action based on the marking of the pipeline; and clearing the marking of the pipeline based on the triggering of the clearing action.

18 . The computer program product of claim 17 , wherein the pipeline is an execution unit pipeline, the event comprises a pipeline flush event or a rescind event, and the event is associated with a programmable instruction operational code, and the triggering of the clearing action is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code.

19 . The computer program product of claim 17 , wherein the clearing action comprises a complete purging of the pipeline.

20 . The computer program product of claim 17 , wherein the repeated resource contention is with respect to a shared resource and triggering the clearing action further comprises confirming that the event has occurred for a predetermined number of times.

Assignees

• IBM

Inventors

• Barak Erez
• Carlough Steven R
• Gonen Eyal
• Haess Juergen
• Mueller Silvia M

Classifications

• G06F11/142

  Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044) · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/2028 Primary

  eliminating a faulty processor or activating a spare · CPC title

• G06F2201/82

  Solving problems relating to consistency · CPC title

• G06F9/3867

  using instruction pipelines · CPC title