Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Patent metadata

Field	Value
Publication number	US-2017192484-A1
Application number	US-201614986738-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

First claim

What is claimed is:

1 . An apparatus for dynamic clock and voltage scaling, comprising:
a first hardware counter configured to count, during a current program execution phase, each cycle in which a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss; a second hardware counter configured to count a total number of cycles in the current program execution phase; a third hardware counter configured to count committed instructions; and a processor configured to:
read the first hardware counter and the second hardware counter in response to the third hardware counter reaching a threshold value;
measure a stall fraction during the current program execution phase, wherein the measured stall fraction comprises a first value read from the first hardware counter during the current program execution phase divided by a second value read from the second hardware counter during the current program execution phase;
predict a stall fraction in a next program execution phase based on the measured stall fraction during the current program execution phase and a predicted stall fraction for the current program execution phase; and
invoke a dynamic clock and voltage scaling (DCVS) module to apply a frequency setting and a voltage setting during the next program execution phase based on the predicted stall fraction in the next program execution phase.

2 . The apparatus recited in claim 1 , wherein the processor is configured to predict the stall fraction in the next program execution phase according to an exponential moving average based on the formula:
PredStall n+1 =α*Stall n +(1−α)*PredStall n
where α is a constant value, Stall n is the measured stall fraction during the current program execution phase, and PredStall n is the predicted stall fraction for the current program execution phase.

3 . The apparatus recited in claim 2 , wherein the processor is further configured to calculate the predicted stall fraction for the current program execution phase in an immediately preceding program execution phase.

4 . The apparatus recited in claim 2 , wherein the constant value α is a programmable and empirically determined constant.

5 . The apparatus recited in claim 1 , wherein the processor is further configured to map the predicted stall fraction in the next program execution phase to the frequency setting and the voltage setting to be applied during the next program execution phase.

6 . The apparatus recited in claim 1 , wherein the processor is further configured to:
compare the predicted stall fraction in the next program execution phase to different thresholds that correspond to different frequency and voltage settings; and map the predicted stall fraction in the next program execution phase to one of the different frequency and voltage settings that maximizes power savings and minimizes performance loss at the predicted stall fraction.

7 . The apparatus recited in claim 1 , wherein the second hardware counter counts the total number of cycles in the current program execution phase needed to retire the committed instructions counted at the third hardware counter in the current program execution phase.

8 . The apparatus recited in claim 7 , wherein the committed instructions counted at the third hardware counter equals the threshold value when the first hardware counter and the second hardware counter are read.

9 . The apparatus recited in claim 7 , wherein the third hardware counter is incremented to count the committed instructions to configure a polling interval used at the processor to read the first hardware counter and the second hardware counter.

10 . The apparatus recited in claim 1 , wherein the processor is further configured to:
assert an interrupt to read the first hardware counter and the second hardware counter in response to the third hardware counter reaching the threshold value; and reset the first hardware counter, the second hardware counter, and the third hardware counter upon reading the first and second hardware counters.

11 . An apparatus, comprising:
means for counting, during a current program execution phase, a number of cycles in which a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss; means for measuring a stall fraction during the current program execution phase, wherein the measured stall fraction comprises the number of cycles during the current program execution phase in which a dispatch stall occurred and the oldest instruction in the load queue was a last-level cache miss divided by total cycles counted in the current program execution phase; means for predicting a stall fraction in a next program execution phase based on the measured stall fraction during the current program execution phase and a predicted stall fraction for the current program execution phase; and means for invoking a dynamic clock and voltage scaling (DCVS) module to apply a frequency setting and a voltage setting during the next program execution phase based on the predicted stall fraction in the next program execution phase.

12 . The apparatus recited in claim 11 , wherein the stall fraction in the next program execution phase is predicted according to the formula:
PredStall n+1 =α*Stall n +(1−α)*PredStall n
where α is a constant value, Stall n is the measured stall fraction during the current program execution phase, and PredStall n is the predicted stall fraction for the current program execution phase.

13 . The apparatus recited in claim 12 , wherein the predicted stall fraction for the current program execution phase is calculated in an immediately preceding program execution phase.

14 . The apparatus recited in claim 12 , wherein the constant value α is a programmable and empirically determined constant.

15 . The apparatus recited in claim 11 , further comprising means for mapping the predicted stall fraction in the next program execution phase to the frequency setting and the voltage setting to be applied during the next program execution phase.

16 . The apparatus recited in claim 11 , further comprising:
means for comparing the predicted stall fraction in the next program execution phase to different thresholds that correspond to different frequency and voltage settings; and means for mapping the predicted stall fraction in the next program execution phase to one of the different frequency and voltage settings that maximizes power savings and minimizes performance loss at the predicted stall fraction.

17 . The apparatus recited in claim 11 , further comprising means for reading the counted number of cycles in which a dispatch stall occurred and the oldest instruction in the load queue was a last-level cache miss in response to a number of committed instructions counted in the current program execution phase reaching a threshold.

18 . The apparatus recited in claim 17 , further comprising means for resetting the counted number of cycles during the current program execution phase in which a dispatch stall occurred and the oldest instruction in the load queue was a last-level cache miss, the total cycles counted in the current program execution phase, and the number of committed instructions counted in the current program subsequent to the reading.

19 . A method for dynamic clock and voltage scaling, comprising:
counting, during a current program execution phase, a number of cycles in which a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss; measuring

Assignees

• Qualcomm Inc

Inventors

• Priyadarshi Shivam
• Krishna Anil
• Damodaran Raguram
• Bridges Jeffrey Todd
• Wells Ryan
• Gargash Norman
• Smith Rodney Wayne

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3228 Primary

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title