Driving circuit, array substrate and display device

Patent metadata

Field	Value
Publication number	US-2017178583-A1
Application number	US-201615188631-A
Country	US
Kind code	A1
Filing date	Jun 21, 2016
Priority date	Dec 18, 2015
Publication date	Jun 22, 2017
Grant date	—

Abstract

A driving circuit, an array substrate and a display device are provided. The driving circuit includes a plurality of cascaded shift registers. Each shift register includes a plurality of transistors and at least one capacitor, and a channel width-to-length ratio of at least one transistor is determined by a preset number of pixels in a pixel row driven by the corresponding shift register.

First claim

What is claimed is:

1 . A driving circuit, comprising:
a plurality of cascaded shift registers, wherein each shift register includes a plurality of transistors and at least one capacitor, and a channel width-to-length ratio of at least one transistor is determined by a preset number of pixels in a pixel row driven by the corresponding shift register.

2 . The driving circuit according to claim 1 , wherein:
the channel width-to-length ratio of the at least one transistor is positively correlated with the preset number of the pixels in the pixel row driven by the corresponding shift register.

3 . The driving circuit according to claim 1 , wherein:
the shift register includes at least one pull-up transistor.

4 . The driving circuit according to claim 3 , wherein:
the channel width of the pull-up transistor in the N th stage shift register is determined by the following formula:

W
N

=

W
1

+

W
1

×

(

L
N
2

-

L
1
2

L
1
2

)

wherein W 1 is a channel width of the pull-up transistor in the first stage shift register, L 1 is the total length of the pixel row driven by the first stage shift register, L N is the total length of the pixel row driven by the N th stage shift register Stage N, N is a positive integer larger than 1.

5 . The driving circuit according to claim 4 , wherein:
the total length of the pixel row is a length of the preset number of pixels in the pixel row.

6 . The driving circuit according to claim 1 , wherein the shift register further includes:
a first transistor having a second electrode connected to a junction P, and a gate electrode connected to an output terminal of the shift register one stage lower; a second transistor having a first electrode connected to the junction P, and a gate electrode connected to an output terminal of the shift register one stage higher; a third transistor having a first electrode connected to the junction P, a gate electrode connected to a junction Q, and a second electrode connected to a low voltage signal; a fourth transistor having a gate electrode connected to the junction P, a first electrode connected to a junction Q, and a second electrode connected to the low voltage signal; a fifth transistor having a gate electrode connected to the junction P, and a first electrode connected to an output terminal of the shift register; a sixth transistor having a gate electrode connected to the junction P, a first electrode connected to the output terminal of the shift register, and a second electrode connected to the low voltage signal; a seventh transistor having a first electrode connected to the output terminal of the shift register, and a second electrode connected to the low voltage signal; a first capacitor having a first plate connected to a junction Q and a second plate connected to the output terminal of the shift register; and a second capacitor having a first plate connected to the junction P, wherein the channel width-to-length ratio of the fifth transistor is determined by the preset number of the pixels in the pixel row driven by the shift register.

7 . The driving circuit according to claim 6 , wherein:
the fifth transistor is the at least one pull-up transistor.

8 . The driving circuit according to claim 6 , wherein:
the gate electrode of the first transistor in the first shift register is connected to an external driving signal.

9 . The driving circuit according to claim 6 , wherein the shift register further includes:
a virtual shift register, wherein the gate electrode of the second transistor in the last shift register is connected to an output terminal of the virtual shift register.

10 . The driving circuit according to claim 6 , wherein:
the first electrode of the first transistor is connected to a high voltage signal; and the second electrode of the second transistor is connected to the low voltage signal.

11 . The driving circuit according to claim 6 , wherein:
the first electrode of the first transistor is connected to the low voltage signal; and the second electrode of the second transistor is connected to the high voltage signal.

12 . The driving circuit according to claim 6 , wherein:
the second plate of the first capacitor and the second electrode of the fifth transistor are connected to a first clock signal; and the gate electrode of the seventh transistor is connected to a second clock signal CK, wherein the first clock signal and the second clock signal are two phase reversed clock signals.

13 . An array substrate, comprising:
a non-rectangular pixel array; and a driving circuit including a plurality of cascaded shift registers, wherein each shift register includes a plurality of transistors and at least one capacitor, a channel width-to-length ratio of at least one transistor is determined by a preset number of pixels in a pixel row driven by the corresponding shift register.

14 . The array substrate according to claim 13 , wherein:
the driving circuit is integrated on the array substrate.

15 . A display device, comprising:
an array substrate including a non-rectangular pixel array and a driving circuit having a plurality of cascaded shift registers, wherein each shift register includes a plurality of transistors and at least one capacitor, a channel width-to-length ratio of at least one transistor is determined by a preset number of pixels in a pixel row driven by the corresponding shift register.

Assignees

• Shanghai Avic Opto Electronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Zhang Weiwei
• Wang Meilin
• Li Jun

Classifications

• G09G2300/0404

  Matrix technologies · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title