Display panel structure

Patent metadata

Field	Value
Publication number	US-9620077-B2
Application number	US-201514676167-A
Country	US
Kind code	B2
Filing date	Apr 1, 2015
Priority date	May 9, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A display panel structure includes a substrate, plural gate lines and data lines arranged on the substrate, plural pixel units, and plural dummy pixel units. The substrate has a display region and a peripheral region surrounding the display region. The gate lines and data lines are extended from the display region to the peripheral region. The pixel units are disposed at the display region. The dummy pixel units are disposed at the peripheral region, and include a first region, a second region, and a third region. The dummy pixel units of the first region and the second region are arranged along a first direction and a second direction, respectively. The dummy pixel units of the third region are arranged between the first and second regions. The dummy pixel units of the third region include one of the gate lines and one of the data lines.

First claim

What is claimed is:

1. A display panel structure, comprising:
a substrate having a display region and a peripheral region, the peripheral region surrounding the display region;
a plurality of gate lines arranged in parallel on the substrate along a first direction, wherein the plurality of gate lines are extended from the display region to the peripheral region;
a plurality of data lines arranged in parallel on the substrate along a second direction, which is not parallel with the first direction, wherein the plurality of data lines are extended from the display region to the peripheral region;
a plurality of pixel units disposed at the display region, each of the plurality of the pixel units being defined by two adjacent gate lines and two adjacent data lines; and
a plurality of dummy pixel units disposed at the peripheral region including a first region of the plurality of dummy pixel units, a second region of the a plurality of dummy pixel units, and a third region of the a plurality of dummy pixel units, wherein the dummy pixel units of the first region are arranged along the first direction, the dummy pixel units of the second region are arranged along the second direction, and the dummy pixel units of the third region are arranged between the first region and the second region, and wherein the dummy pixel units of the third region include one of the plurality of gate lines and one of the plurality of data lines,
wherein at least one of the dummy pixel units of the third region has a thin film transistor including a source electrode and a drain electrode, the drain electrode and the source electrode are disconnected to the data line.

2. The display panel structure as claimed in claim 1 , further comprising:
a gate driver for driving the plurality of gate lines; and
a data driver for driving the plurality of data lines.

3. The display panel structure as claimed in claim 1 , wherein each of the dummy pixel units of the third region has a thin film transistor including a gate electrode connected with one of the plurality of gate lines.

4. The display panel structure as claimed in claim 1 , wherein each of the dummy pixel units of the third region has a thin film transistor including a floating gate electrode.

5. The display panel structure as claimed in claim 1 , further comprising:
at least one dummy gate line arranged on the substrate along the first direction for passing through the dummy pixel units of the first region, the dummy gate line being disposed at the peripheral region; and
at least one dummy data line arranged on the substrate along the second direction for passing through the dummy pixel units of the second region, the dummy data line being disposed at the peripheral region.

6. The display panel structure as claimed in claim 5 , wherein each of the dummy pixel units of the first region has at least one thin film transistor including a gate electrode connected with the dummy gate line and a drain electrode or a source electrode connected with one of the plurality of data lines.

7. The display panel structure as claimed in claim 6 , wherein each of the dummy pixel units of the second region has at least one thin film transistor including a gate electrode connected with one of the plurality of gate lines and a drain electrode or a source electrode connected with the dummy data line.

8. The display panel structure as claimed in claim 6 , wherein the dummy gate line further passes through the dummy pixel units of the second region.

9. The display panel structure as claimed in claim 8 , wherein each of the dummy pixel units of the second region has at least one thin film transistor including a gate electrode connected with the dummy gate line and a drain electrode or a source electrode connected with the dummy data line.

10. The display panel structure as claimed in claim 5 , wherein the dummy gate line is connected with one of the plurality of gate lines.

11. The display panel structure as claimed in claim 5 , wherein each of the dummy pixel units of the third region has a first thin film transistor and a second thin film transistor.

12. The display panel structure as claimed in claim 11 , wherein the first thin film transistor includes a gate electrode connected with the dummy gate line and a drain electrode or a source electrode connected with the dummy data line or a floating drain electrode or a floating source electrode, and the second thin film transistor includes a gate electrode connected with one of the plurality of gate lines and a floating drain electrode or a floating source electrode.

13. A display panel structure, comprising:
a substrate having a display region and a peripheral region, the peripheral region surrounding the display region;
a plurality of gate lines arranged in parallel on the substrate along a first direction, wherein the plurality of gate lines are extended from the display region to the peripheral region;
a plurality of data lines arranged in parallel on the substrate along a second direction, which is not parallel with the first direction, wherein the plurality of data lines are extended from the display region to the peripheral region;
a plurality of pixel units disposed at the display region, each of the plurality of the pixel units being defined by two adjacent gate lines and two adjacent data lines; and
a plurality of dummy pixel units disposed at the peripheral region including a first region of the plurality of dummy pixel units, a second region of the a plurality of dummy pixel units, and a third region of the a plurality of dummy pixel units, wherein the dummy pixel units of the first region are arranged along the first direction, the dummy pixel units of the second region are arranged along the second direction, and the dummy pixel units of the third region are arranged between the first region and the second region, and wherein the dummy pixel units of the third region include one of the plurality of gate lines and one of the plurality of data lines, a dummy gate line includes at least one bridge to connect the dummy pixel units of the first region and the dummy pixel units of the second region, and the dummy gate line is across and intersected with at least one of the plurality of gate lines.

14. The display panel structure as claimed in claim 13 , wherein each of the dummy pixel units of the first region has at least one thin film transistor including a gate electrode connected with the dummy gate line and a floating drain electrode or a floating source electrode.

15. The display panel structure as claimed in claim 14 , wherein each of the dummy pixel units of the second region has at least one thin film transistor including a gate electrode connected with one of the plurality of gate lines and a drain electrode or a source electrode connected with the dummy data line.

16. The display panel structure as claimed in claim 14 , wherein the dummy gate line further passes through the dummy pixel units of the second region.

17. The display panel structure as claimed in claim 16 , wherein each of the dummy pixel units of the second region has at least one thin film transistor including a gate electrode connected with the dummy gate line and a drain electrode or a source electrode connected with the dummy data line.

Assignees

• Innolux Corp

Inventors

• Shih Chien-Feng
• Chiu Yu-Hsiang
• Chang Liang-Yun
• Huang Sheng-Feng

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• H01L27/124

  Electricity · mapped topic

• G09G2300/0413

  Details of dummy pixels or dummy lines in flat panels · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H01L27/0292

  Electricity · mapped topic