Method of fabricating substrate structure

Patent metadata

Field	Value
Publication number	US-2017171981-A1
Application number	US-201615393429-A
Country	US
Kind code	A1
Filing date	Dec 29, 2016
Priority date	Sep 12, 2014
Publication date	Jun 15, 2017
Grant date	—

Abstract

The present invention provides a substrate structure and a method of fabricating the substrate structure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulating protection layer, and removing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.

First claim

1 . A method of fabricating a substrate structure, comprising:
forming on a first carrier a first wiring layer having opposing first and second surfaces, with the first surface of the first wiring layer coupled to the first carrier; forming on the second surface of the first wiring layer a dielectric layer that has at least one hole exposing a portion of the first wiring layer; forming a second wiring layer on the dielectric layer, and forming in the at least one hole, from which the portion of the first wiring layer is exposed, at least a conductive via that is electrically connected to the second wiring layer and the first wiring layer; forming on the dielectric layer and the second wiring layer an insulating protection layer that has at least one opening that exposes a portion of the second wiring layer; forming a second carrier on the insulating protection layer; and removing the first carrier.

2 . The method of claim 1 , wherein the first carrier comprises a main body and a seed layer formed on the main body, and the first wiring layer is formed on the seed layer.

3 . The method of claim 2 , wherein the first wiring layer is formed by:
forming a patterned resist layer on the seed layer, with a portion of the seed layer exposed from the patterned resist layer and the first wiring layer formed on the exposed portion of the first seed layer; and removing the patterned resist layer.

4 . The method of claim 1 , wherein the second wiring layer and the conductive via are formed by:
forming the dielectric layer on the second surface of the first wiring layer; forming a second seed layer on the dielectric layer; laser drilling or mechanical drilling the second seed layer and the dielectric layer to form at least one hole that exposes the portion of the first wiring layer; and forming the second wiring layer on the second seed layer, and forming the at least a conductive via in the at least one hole, from which the portion of the first wiring layer is exposed.

5 . The method of claim 4 , further comprising, prior to forming the second wiring layer, forming a patterned resist layer on the second seed layer, with a portion of the second seed layer exposed from the patterned resist layer and the second wiring layer formed on the exposed portion of the second seed layer, and removing the patterned resist layer.

6 . The method of claim 1 , wherein the insulating protection layer is made of a solder mask.

7 . The method of claim 1 , wherein the second carrier is made of an adhesive material or a release material.

8 . The method of claim 1 , wherein the second carrier is in contact with and carries the insulating protection layer, and the opening is filled with a portion of the second carrier.

9 . The method of claim 1 , wherein the first carrier has two opposing sides, and the first wiring layer, the dielectric layer, the second wiring layer, the insulating protection layer and the second carrier are formed on the two sides of the first carrier.

10 - 15 . (canceled)

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Lin Chun-Hsien
• Chiu Shih-Chao
• Pai Yu-Cheng
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K3/188

  by direct electroplating · CPC title

• H05K3/28

  Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} · CPC title

• H05K3/0026

  by laser ablation · CPC title

• H05K3/007 Primary

  Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence) · CPC title