Structure design generation for fixing metal tip-to-tip across cell boundary

Patent metadata

Field	Value
Publication number	US-2017168386-A1
Application number	US-201514967103-A
Country	US
Kind code	A1
Filing date	Dec 11, 2015
Priority date	Dec 11, 2015
Publication date	Jun 15, 2017
Grant date	—

Abstract

A method for structure design including detecting, by a processor, a tip-to-tip (T2T) structure design violation for a metal layer above (Ma) a via (Vx) at a tip of the Ma for a design file layout for the structure. Upon detection of the T2T structure design violation, retargeting, by the processor, of the Vx based on adjusting of both the Ma and a metal layer (Mb) below the Vx that connects the Ma through the Vx for the design file layout of the structure to improve performance of the structure based on fixing metal tip or metal ending across cell boundaries.

First claim

What is claimed is:

1 . A method for semiconductor structure design comprising:
detecting, by a processor, a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for a design file layout for the structure; and upon detection of the T2T structure design violation, retargeting, by the processor, of the Vx based on adjusting any of the Ma, a metal layer (Mb) below the Vx that connects the Ma through the Vx and the Vx that connects the Ma and the Mb for the design file layout of the structure to improve performance of the structure based on fixing metal tip or metal ending across cell boundaries.

2 . The method of claim 1 , further comprising:
determining whether the Vx is at a first metal line end (LE); upon the Vx being at the metal LE, setting the T2T design value for the design file layout for the structure; and analyzing the Ma, the Vx and the Mb to determine whether the Mb is at a second metal LE.

3 . The method of claim 2 , further comprising:
upon the Vx not being at the first metal LE, relaxing T2T requirement values for the design file layout for the structure.

4 . The method of claim 2 , further comprising:
upon a determination that the Mb is not at the second metal LE, determining the Mb available space at a common edge (E_VxMb) between the Mb and the Vx; and upon a determination that the Mb available space at E_VxMb is greater than a minimum allowable space for the Mb, jogging a design value for the Mb, retargeting a design value for the Vx and executing a design process or using a first set of predetermined design values, otherwise upon a determination that the Ma available space at a common edge (E_VxMa) between the Ma and the Vx is greater than a minimum allowable space for the Ma, jogging a design value for the Ma, retargeting the design value for the Vx and executing the design process or using a second set of predetermined design values.

5 . The method of claim 2 , further comprising:
upon a determination that the Mb is at the second metal LE, upon a determination that the Ma available space at E_VxMa is greater than the minimum allowable space for the Ma and the Mb available space at E_VxMb is greater than the Mb minimum space, jogging the design value for the Ma and for the Mb, retargeting the design value for the Vx and executing the design process or using a third set of predetermined design values, otherwise inserting a dummy track into the design file layout for the structure.

6 . The method of claim 1 , wherein the retargeting of the Vx comprises retargeting metal below the Vx in a vertical direction to avoid Vx metal shorting.

7 . The method of claim 5 , further comprising:
upon a determination that a resulting design file layout for the structure falls outside of a three sigma area for the Vx, re-determining whether the Mb is at the second metal LE, otherwise outputting a final design file layout for the structure.

8 . A computer program product for generating a semiconductor structure design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:
detect, by the computer, a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for a design file layout for a structure; and upon detection of the T2T structure design violation, retarget, by the computer, of the Vx based on adjusting any of the Ma, a metal layer (Mb) below the Vx that connects the Ma through the Vx and the Vx that connects the Ma and the Mb for the design file layout of the structure to improve performance of the structure based on fixing metal tip or metal ending across cell boundaries.

9 . The computer program product of claim 8 , wherein the program instructions executable by the computer to further cause the computer to:
determine, by the computer, whether the Vx is at a first metal line end (LE); upon the Vx being at the metal LE, set, by the computer, the T2T design value for the design file layout for the structure; and analyze, by the computer, the Ma, the Vx and the Mb to determine whether the Mb is at a second metal LE.

10 . The computer program product of claim 9 , wherein the program instructions executable by the computer to further cause the computer to:
upon the Vx not being at the first metal LE, relax, by the computer, T2T requirement values for the design file layout for the structure.

11 . The computer program product of claim 9 , wherein the program instructions executable by the computer to further cause the computer to:
upon a determination that the Mb is not at the second metal LE, determine, by the computer, the Mb available space at a common edge (E_VxMb) between the Mb and the Vx; and upon a determination that the Mb available space at E_VxMb is greater than a minimum allowable space for the Mb, jog, by the computer, a design value for the Mb, retarget a design value for the Vx and execute, by the computer, a design process or using a first set of predetermined design values, otherwise upon a determination that the Ma available space at a common edge (E_VxMa) between the Ma and the Vx is greater than a minimum allowable space for the Ma, jog, by the computer, a design value for the Ma, retarget the design value for the Vx and execute, by the computer, the design process or using a second set of predetermined design values.

12 . The computer program product of claim 9 , wherein the program instructions executable by the computer to further cause the computer to:
upon a determination that the Mb is at the second metal LE and upon a determination that the Ma available space at E_VxMa is greater than the minimum allowable space for the Ma and the Mb available space at E_VxMb is greater than the Mb minimum space, jog, by the computer, the design value for the Ma and for the Mb, retarget, by the computer, the design value for the Vx and execute, by the computer, the design process or using a third set of predetermined design values, otherwise insert, by the computer, a dummy track into the design file layout for the structure.

13 . The computer program product of claim 8 , wherein the retarget of the Vx comprises retarget of metal below the Vx in a vertical direction to avoid Vx metal shorting.

14 . The computer program product of claim 13 , wherein the program instructions executable by the computer to further cause the computer to:
upon a determination that a resulting design file layout for the structure falls outside of a three sigma area for the Vx, re-determine, by the computer, whether the Mb is at the second metal LE, otherwise output, by the computer, a final design file layout for the structure.

15 . A method for generating a semiconductor structure design comprising:
detecting, by a processor, a structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for generating a design file layout for the structure; and upon detection of the structure design violation, retargeting, by the processor, of design values for the Vx based on adjusting design values for any of the Ma, a metal layer (Mb) below the Vx that connects the Ma through the Vx and the Vx that connects the Ma and the Mb for the design file layout of the structure, wherein adjusting design values of both the Ma and the Mb provide fixing metal tip or metal ending across cell boundaries.

16 . The method of claim 15 , further co

Assignees

• IBM

Inventors

• Han Geng
• Shao Dongbing

Classifications

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5072

  Physics · mapped topic