Method of manufacturing a semiconductor structure

Patent metadata

Field	Value
Publication number	US-2017162402-A1
Application number	US-201514960977-A
Country	US
Kind code	A1
Filing date	Dec 7, 2015
Priority date	Dec 7, 2015
Publication date	Jun 8, 2017
Grant date	—

Abstract

A method of manufacturing a semiconductor structure is provided. First, a preliminary structure is provided. The preliminary structure has a first region and a second region, and the preliminary structure comprises a plurality of features in the first region. Then, a first polish stop layer is formed on the preliminary structure. The first polish stop layer comprises a concave portion in the second region, and the concave portion defines an opening. A first overlying layer is formed on the first polish stop layer. Thereafter, a second polish stop layer is formed on the first overlying layer. The second polish stop layer has a graduated change in composition. The second polish stop layer comprises a concave portion at least partially formed in the opening. A second overlying layer is formed on the second polish stop layer.

First claim

1 . A method of manufacturing a semiconductor structure, comprising:
providing a preliminary structure, wherein the preliminary structure has a first region and a second region, and the preliminary structure comprises a plurality of features in the first region; forming a first polish stop layer on the preliminary structure, wherein the first polish stop layer comprises a concave portion in the second region, and the concave portion defines an opening; forming a first overlying layer on the first polish stop layer; forming a second polish stop layer on the first overlying layer, wherein the second polish stop layer is formed of silicon oxynitride and has a graduated change in a molar ratio of silicon oxide and silicon nitride, and the second polish stop layer comprises a concave portion at least partially formed in the opening; forming a second overlying layer on the second polish stop layer; and performing a CMP process such that the second overlying layer and the first overlying layer in the first region are completely removed.

2 . The method according to claim 1 , wherein the second polish stop layer has a bottom surface in the second region lower than a top surface of the first polish stop layer in the first region.

3 . The method according to claim 1 , wherein the first overlying layer and the second overlying layer are formed of a same material.

4 . The method according to claim 1 , wherein a material of the second polish stop layer is chosen according to materials of the first polish stop layer as well as the first and second overlying layers.

5 . The method according to claim 1 , wherein the first polish stop layer is formed of silicon nitride, and the first and second overlying layers are formed of oxide.

6 . The method according to claim 1 , wherein a molar ratio of silicon oxide and silicon nitride of the second polish stop layer at an interface of the second polish stop layer and the first overlying layer is closer to a molar ratio of silicon oxide and silicon nitride of the first overlying layer than a molar ratio of silicon oxide and silicon nitride of the second polish stop layer at a middle portion of the second polish stop layer, and a molar ratio of silicon oxide and silicon nitride of the second polish stop layer at an interface of the second polish stop layer and the second overlying layer is closer to a molar ratio of silicon oxide and silicon nitride of the second overlying layer than the molar ratio of silicon oxide and silicon nitride of the second polish stop layer at the middle portion of the second polish stop layer.

7 . The method according to claim 1 , wherein the first overlying layer has a thickness substantially equal to a depth of the opening.

8 . (canceled)

9 . The method according to claim 1 , wherein the features in the first region are fins.

10 . The method according to claim 9 , wherein the preliminary structure further comprises:
a substrate, wherein the fins are formed on the substrate; a dielectric layer formed on the substrate between the fins; and a fin-embedded layer formed on the dielectric layer, the fin-embedded layer covering the fins.

Assignees

• United Microelectronics Corp

Inventors

• Tsai Fu-Shou
• Li Yu-Ting
• Hsu Li-Chieh
• Li Kun-Ju
• Lin Chih-Hsun
• Huang Po-Cheng
• Liu Yi-Liang
• Lin Wen-Chin

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10P52/403 Primary

  of conductive or resistive materials · CPC title

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H01L21/7684

  Electricity · mapped topic