Flash memory device including address mapping for deduplication, and related methods

Patent metadata

Field	Value
Publication number	US-2017161202-A1
Application number	US-201514957114-A
Country	US
Kind code	A1
Filing date	Dec 2, 2015
Priority date	Dec 2, 2015
Publication date	Jun 8, 2017
Grant date	—

Abstract

A data storage device includes a flash memory that includes blocks of physical pages that include physical sectors configured to store data therein. A memory control unit, including a flash translation layer (FTL), is configured to receive write data sectors to be stored in the flash memory, determine at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation, and store the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory. Logical-to-physical addresses of the reference data sector and the corresponding matched data sector are mapped in the FTL, and physical-to-logical information regarding the corresponding matched data sector is written in a designated physical-to-logical information area of the flash memory. The physical-to-logical information area may be a metadata area of a physical sector, an adjacent physical sector in a same page, a last sector of a block or a dedicated block of the flash memory.

First claim

1 . A method of operating a data storage device including a control unit and a flash memory that includes blocks of physical pages that include physical sectors to store data therein, the method comprising:
receiving write data sectors to be stored in the flash memory; determining at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation; storing the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory; mapping logical-to-physical addresses of the reference data sector and the corresponding matched data sector in a flash translation layer (FTL) of the control unit; and writing physical-to-logical information regarding the corresponding matched data sector in a designated physical-to-logical information area of the flash memory.

2 . The method of claim 1 , wherein the physical-to-logical information comprises logical addresses of the reference data sector and the corresponding matched data sector; and wherein the designated physical-to-logical information area comprises a metadata area in the physical sector storing the reference data sector.

3 . The method of claim 2 , wherein the deduplication operation includes the use of a buffer for determining the matched data sector before the reference data sector is stored in the physical sector of the physical page of the block in the flash memory.

4 . The method of claim 1 , wherein the physical-to-logical information comprises a logical address of the corresponding matched data sector; wherein a logical address of the reference data sector is written to a metadata area in the physical sector storing the reference data sector; and
wherein the designated physical-to-logical information area comprises an adjacent physical sector, in the same physical page of the physical sector storing the reference data sector.

5 . The method of claim 4 , wherein the at least one matched data sector comprises a plurality of matched data sectors; and wherein writing physical-to-logical information comprises writing logical addresses of the plurality of matched data sectors in the adjacent physical sector which defines an address sector of the physical page.

6 . The method of claim 5 , wherein the deduplication operation includes the use of a buffer for determining the plurality of matched data sectors before the reference data sector is stored in the physical sector of the physical page of the block in the flash memory.

7 . The method of claim 1 , wherein the physical-to-logical information comprises an inverse-mapping-sector defined by a physical address of the physical sector storing the reference data sector, and logical addresses of the reference data sector and the corresponding matched data sector; and wherein the designated physical-to-logical information area comprises a last physical sector in the block and storing the inverse-mapping-sector.

8 . The method of claim 7 , wherein the physical address in the inverse-mapping-sector is defined by an offset relative to a first physical sector in the block.

9 . The method of claim 1 , wherein the physical-to-logical information comprises an inverse-mapping-sector defined by a physical address of the physical sector storing the reference data sector, and logical addresses of the reference data sector and the corresponding matched data sector; and wherein the designated physical-to-logical information area comprises a dedicated block of the flash memory configured to store inverse-mapping-sectors for blocks of the flash memory.

10 . The method of claim 9 , further comprising storing a mapping of the inverse-mapping-sectors of the dedicated block in a RAM of the control unit.

11 . The method of claim 10 , further comprising performing garbage collection on the flash memory including reading the mapping of the inverse-mapping-sectors from RAM, reading the inverse mapping sectors from the flash memory, and reading the logical-to-physical addresses from the FTL.

12 . The method of claim 1 , further comprising performing garbage collection on the flash memory including reading the physical-to-logical information from the designated physical-to-logical information area of the flash memory, and reading the logical-to-physical addresses from the FTL.

13 . The method of claim 1 , wherein the physical pages include an array of memory cells, including at least one of single-level cells (SLC), multi-level cells (MLC) and triple-level cells (TLC), coupled between word lines and bit lines.

14 . A data storage system comprising:
a flash memory including blocks of physical pages that include physical sectors configured to store data therein; and a memory control unit including a flash translation layer (FTL), and configured to
receive write data sectors to be stored in the flash memory,
determine at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation,
store the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory,
map logical-to-physical addresses of the reference data sector and the corresponding matched data sector in the FTL; and
write physical-to-logical information regarding the corresponding matched data sector in a designated physical-to-logical information area of the flash memory.

15 . The data storage system of claim 14 , wherein the physical-to-logical information comprises logical addresses of the reference data sector and the corresponding matched data sector; and wherein the designated physical-to-logical information area comprises a metadata area in the physical sector storing the reference data sector.

16 . The data storage system of claim 15 , wherein the memory control unit includes a buffer; and wherein the deduplication operation includes the use of the buffer for determining the matched data sector before the reference data sector is stored in the physical sector of the physical page of the block in the flash memory.

17 . The data storage system of claim 14 , wherein the physical-to-logical information comprises a logical address of the corresponding matched data sector; wherein the memory control unit is configured to write a logical address of the reference data sector to a metadata area in the physical sector storing the reference data sector; and wherein the designated physical-to-logical information area comprises an adjacent physical sector, in the same physical page of the physical sector storing the reference data sector.

18 . The data storage system of claim 17 , wherein the at least one matched data sector comprises a plurality of matched data sectors; and wherein the memory control unit is configured to write physical-to-logical information as logical addresses of the plurality of matched data sectors in the adjacent physical sector which defines an address sector of the physical page.

19 . The data storage system of claim 18 , wherein the memory control unit includes a buffer; and wherein the deduplication operation includes the use of the buffer for determining the plurality of matched data sectors before the reference data sector is stored in the physical sector of the physical page of the block in the flash memory.

20 . The data storage system of claim 14 , wherein the physical-to-logical information comprises an inverse-mapping-sector defined by a physical address of the physical sector stor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Erez Elona
• Dor Avner
• Kong Jun Jin

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/1024

  Latency reduction · CPC title