Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-2017125408-A1
Application number	US-201615335984-A
Country	US
Kind code	A1
Filing date	Oct 27, 2016
Priority date	Oct 30, 2015
Publication date	May 4, 2017
Grant date	—

Abstract

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

First claim

1 . A semiconductor device comprising:
a gate insulating layer on a substrate; and a gate electrode structure on the gate insulating layer, wherein the gate electrode structure comprises a lower conductive layer and an upper conductive layer sequentially stacked on the gate insulating layer and a silicon oxide layer between the lower conductive layer and the upper conductive layer, and the lower conductive layer comprises a barrier metal layer.

2 . The semiconductor device of claim 1 , wherein the gate electrode structure further comprises a semiconductor liner between the silicon oxide layer and the lower conductive layer.

3 . The semiconductor device of claim 2 , wherein the semiconductor liner comprises a silicon layer.

4 . The semiconductor device of claim 1 , further comprising an interlayer insulating layer on the substrate,
wherein the interlayer insulating layer comprises a trench, and wherein the gate insulating layer extends along a sidewall and a bottom surface of the trench.

5 .- 13 . (canceled)

14 . A semiconductor device comprising:
a substrate comprising a first region and a second region; a first gate insulating layer on the first region of the substrate; a first gate electrode structure on the first gate insulating layer, the first gate electrode structure comprising a first lower conductive layer, a first silicon oxide layer and a first upper conductive layer sequentially stacked on the first gate insulating layer, and the first lower conductive layer comprising a first barrier metal layer; a second gate insulating layer on the second region of the substrate; and a second gate electrode structure on the second gate insulating layer, the second gate electrode structure comprising a second lower conductive layer and a second upper conductive layer sequentially stacked on the second gate insulating layer.

15 . The semiconductor device of claim 14 , wherein the second gate electrode structure further comprises a second silicon oxide layer.

16 . The semiconductor device of claim 15 , wherein the second silicon oxide layer is disposed between the second lower conductive layer and the second upper conductive layer.

17 . The semiconductor device of claim 15 , wherein the second gate electrode structure further comprises a semiconductor liner between the second silicon oxide layer and the second gate insulating layer.

18 . The semiconductor device of claim 17 , wherein the semiconductor liner does not contact the second gate insulating layer.

19 . The semiconductor device of claim 15 , wherein the second gate electrode structure further comprises a semiconductor liner between the second lower conductive layer and the second upper conductive layer.

20 . The semiconductor device of claim 19 , wherein the second gate electrode structure does not include a silicon oxide layer between the semiconductor liner and the second upper conductive layer.

21 . The semiconductor device of claim 14 , wherein the second gate electrode structure does not include a silicon oxide layer between the second lower conductive layer and the second upper conductive layer.

22 . The semiconductor device of claim 14 , wherein the first gate electrode structure further comprises a semiconductor liner between the first silicon oxide layer and the first lower conductive layer.

23 . The semiconductor device of claim 22 , wherein the semiconductor liner comprises either a silicon layer or a silicon germanium layer.

24 . The semiconductor device of claim 14 , further comprising an interlayer insulating layer on the substrate,
wherein the interlayer insulating layer comprises a first trench and a second trench, wherein the first gate insulating layer extends along a sidewall and a bottom surface of the first trench, and wherein the second gate insulating layer extends along a sidewall and a bottom surface of the second trench.

25 . The semiconductor device of claim 14 , further comprising a first fin-shaped active region protruding from the first region of the substrate and a second fin-shaped active region protruding from the second region of the substrate,
wherein the first gate electrode structure crosses the first fin-shaped active region, and the second gate electrode structure crosses the second fin-shaped active region.

26 .- 31 . (canceled)

32 . A semiconductor device comprising:
an interlayer insulating layer on a substrate, the interlayer insulating layer comprising a trench; a gate insulating layer extending along a sidewall and a bottom surface of the trench; and a gate electrode structure on the gate insulating layer in the trench, wherein the gate electrode structure comprises an insertion insulating layer that is spaced apart from the gate insulating layer and is on the sidewall and the bottom surface of the trench, and wherein the insertion insulating layer comprises an oxide, oxynitride or nitride of a semiconductor material.

33 . The semiconductor device of claim 32 , wherein the insertion insulating layer comprises silicon oxide, silicon oxynitride, silicon nitride and/or germanium oxide.

34 . The semiconductor device of claim 32 , wherein the gate electrode structure further comprises a semiconductor liner between the insertion insulating layer and the gate insulating layer.

35 . The semiconductor device of claim 34 , wherein the semiconductor liner comprises a silicon layer, a silicon germanium layer and/or a germanium layer.

36 .- 58 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Moon-Kyu
• Song Jae-Yeol
• Na Hoon-Joo
• Hwang Yoon-Tae
• Yoon Ki-joong
• Hyun Sang-Jin

Classifications

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10P14/6536

  by exposure to radiation, e.g. visible light · CPC title

• H01L29/4983

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L21/82345

  Electricity · mapped topic