Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016247909-A1
Application number	US-201514847501-A
Country	US
Kind code	A1
Filing date	Sep 8, 2015
Priority date	Feb 19, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

In one embodiment, a semiconductor device includes a substrate, and a gate conductor provided on the substrate. The device further includes a first insulator provided on the gate conductor, a second insulator provided on the first insulator and including an opening, and a third insulator provided on the second insulator and provided in the opening. The device further includes a first contact plug provided in the first and third insulators, positioned in the opening, and electrically connected to the gate conductor.

First claim

1 . A semiconductor device comprising:
a substrate; a gate conductor provided on the substrate; a first insulator provided on the gate conductor; a second insulator provided on the first insulator and including an opening; a third insulator provided on the second insulator and provided in the opening; and a first contact plug provided in the first and third insulators, positioned in the opening, and electrically connected to the gate conductor.

2 . The device of claim 1 , wherein
the first insulator includes a first layer and a second layer provided on the first layer, the second insulator is formed of a same kind of insulator material as the first layer, and the third insulator is formed of a same kind of insulator material as the second layer.

3 . The device of claim 1 , wherein the first contact plug is provided on a gate electrode or a pad electrode included in the gate conductor.

4 . The device of claim 1 , further comprising a second contact plug provided in the second and third insulators on the substrate and electrically connected to the substrate.

5 . The device of claim 4 , wherein the second contact plug is provided on a source or drain diffusion layer of a transistor on the substrate, or on a diffusion layer positioned between transistors on the substrate.

6 . The device of claim 1 , further comprising:
gate conductors provided on the substrate; an air gap provided between the gate conductors under the first, second or third insulator; and a metallic layer provided in the first, second or third insulator above the air gap.

7 . The device of claim 6 , wherein the metallic layer contains tungsten.

8 . The device of claim 6 , wherein
at least one of the gate conductors includes a first portion extending in a first direction and a second portion extending in a second direction that is different from the first direction, and the metallic layer is provided above the air gap in a vicinity of a connection portion between the first portion and the second portion.

9 . The device of claim 8 , wherein a lower face of the metallic layer is separated, by the third insulator, from an upper end of the air gap in the vicinity of the connection portion between the first portion and the second portion.

10 . The device of claim 8 , wherein the air gap includes a first upper end and a second upper end that is lower than the first upper end and positioned in the vicinity of the connection portion between the first portion and the second portion.

11 . A semiconductor device comprising:
a substrate; a charge storage layer provided on the substrate through a first insulator; a gate conductor provided on the charge storage layer through a second insulator, and including a semiconductor layer and a metallic layer on the semiconductor layer; and a third insulator provided on a side face of the metallic layer, and including an upper end that is higher than an upper face of the metallic layer and a lower end that is lower than a lower face of the metallic layer and higher than a lower face of the semiconductor layer.

12 . The device of claim 11 , wherein the metallic layer contains tungsten.

13 . The device of claim 11 , wherein the third insulator contains nitrogen.

14 . The device of claim 11 , further comprising a fourth insulator provided to be in contact with side faces of the charge storage layer and the semiconductor layer.

15 . A method of manufacturing a semiconductor device, comprising:
forming a charge storage layer on a substrate through a first insulator; forming a gate conductor on the charge storage layer through a second insulator, the gate conductor including a semiconductor layer and a metallic layer on the semiconductor layer; forming a first film on side faces of the charge storage layer, the semiconductor layer and the metallic layer; removing the first film from the side face of the metallic layer; forming, after the first film is removed from the side face of the metallic layer, a third insulator on the side face of the metallic layer; and removing, after the third insulator is formed on the side face of the metallic layer, the first film from the side faces of the charge storage layer and the semiconductor layer.

16 . The method of claim 15 , further comprising forming, before the first film is removed from the side face of the metallic layer, a second film on the side faces of the charge storage layer and the semiconductor layer through the first film,
wherein the first film is removed from the side face of the metallic layer in a state where the second film is formed on the side faces of the charge storage layer and the semiconductor layer through the first film.

17 . The method of claim 16 , wherein the second film includes an upper face that is lower than a lower face of the metallic layer and higher than a lower face of the semiconductor layer.

18 . The method of claim 15 , wherein the metallic layer contains tungsten.

19 . The method of claim 15 , wherein the third insulator contains nitrogen.

20 . The method of claim 15 , further comprising forming, after the first film is removed from the side faces of the charge storage layer and the semiconductor layer, a fourth insulator that is in contact with the side faces of the semiconductor layer and the charge storage layer.

Assignees

• Toshiba Kk

Inventors

• Matsuno Koichi

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title