Pixel array substrate and liquid crystal display panel

Patent metadata

Field	Value
Publication number	US-2017082901-A1
Application number	US-201615366726-A
Country	US
Kind code	A1
Filing date	Dec 1, 2016
Priority date	Jan 22, 2013
Publication date	Mar 23, 2017
Grant date	—

Abstract

A pixel array substrate with new pixel design and a liquid crystal display panel with the pixel array substrate are provided. The pixel array substrate includes a plurality of data lines, a plurality of scan lines and a plurality of pixels. Each of the pixels comprises a first electrode, a first connecting line, a second electrode and a second connecting line. The first electrode is electrically connected with corresponding data line and scan line through the first connecting line, and having a slit. The second pixel is electrically connected with corresponding data line and scan line through the second connecting line. At least a part of the second connecting line is exposed by the slit of the first electrode.

First claim

What is claimed is:

1 . A pixel array substrate, comprising:
a plurality of pixels comprising:
a first pixel electrode having a first slit;
a first connecting line electrically connected to the first pixel electrode;
a second pixel electrode; and
a second connecting line, electrically connected to the second pixel electrode, wherein at least a part of the second connecting line is exposed by the first slit of the first pixel electrode, the first pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode, the first slit is substantially positioned between the first sub-pixel electrode and the second sub-pixel electrode, and the first sub-pixel electrode comprises:
a first main electrode;
a second main electrode, the first main electrode and the second main electrode being electrically connected and are substantially orthogonally arranged to define a first area, a second area, a third area and a fourth area;
a plurality of first branch electrodes disposed in the first area;
a plurality of second branch electrodes disposed in the second area;
a plurality of third branch electrodes disposed in the third area; and
a plurality of fourth branch electrodes disposed in the fourth area,
wherein the plurality of first branch electrodes, the plurality of second branch electrodes, the plurality of third branch electrodes and the plurality of fourth branch electrodes are electrically connected with at least one of the first main electrode and the second main electrode, the first branch electrodes are arranged parallel to each other, the second branch electrodes are arranged parallel to each other, the third branch electrodes are arranged parallel to each other and the fourth branch electrodes are arranged parallel to each other, and the plurality of first branch electrodes, the plurality of second branch electrodes, the plurality of third branch electrodes and the plurality of fourth branch electrodes respectively extend to different directions from the first main electrode or the second main electrode.

2 . The pixel array substrate of claim 1 , wherein the first slit is an open slit.

3 . The pixel array substrate of claim 1 , wherein the first slit is a closed slit.

4 . The pixel array substrate of claim 1 , further comprising:
a plurality of data lines; a plurality of scan lines crossed to the plurality of data lines to define a plurality of pixel areas, wherein the pixels are respectively disposed in the plurality of pixel areas, and the first connecting line and the second connecting line are electrically connected to a data line of the plurality of data lines.

5 . The pixel array substrate of claim 4 , wherein the first main electrode is substantially parallel to the first slit, and the distance between the first main electrode and the first slit is greater than that between the first main electrode and the data line of the plurality of data lines.

6 . The pixel array substrate of claim 1 , further comprising:
a plurality of data lines; a plurality of scan lines crossed to the plurality of data lines to define a plurality of pixel areas, wherein the pixels are respectively disposed in the plurality of pixel areas, and the first connecting line and the second connecting line are electrically connected to different data lines of the plurality of data lines.

7 . The pixel array substrate of claim 1 , wherein the first sub-pixel electrode and the second sub-pixel electrode are mirror symmetry structures with respect to the first slit.

8 . The pixel array substrate of claim 1 , wherein each of the pixels further comprises:
a third pixel electrode having a second slit; and a third connecting line electrically connected to the third pixel electrode; wherein at least a part of the second connecting line is exposed by the first slit of the first pixel electrode and the second slit of the third pixel electrode.

9 . The pixel array substrate of claim 8 , further comprising:
a plurality of data lines; a plurality of scan lines crossed to the plurality of data lines to define a plurality of pixel areas, wherein the pixels are respectively disposed in the plurality of pixel areas, and the first connecting line and the third connecting line are electrically connected to a data line of the plurality of data lines.

10 . The pixel array substrate of claim 8 , wherein the third connecting line is disposed on an edge of the first sub-pixel electrode, the third pixel electrode comprises a third sub-pixel electrode and a fourth sub-pixel electrode, the second slit is substantially positioned between the third sub-pixel electrode and the fourth sub-pixel electrode, and the second slit is substantially positioned along the extending line of the first slit, the first sub-pixel electrode and the second sub-pixel electrode are mirror symmetry structures with respect to the first slit, the third sub-pixel electrode and the fourth sub-pixel electrode are mirror symmetry structures with respect to the second slit.

11 . The pixel array substrate of claim 10 , wherein the third sub-pixel electrode and the fourth sub-pixel electrode respectively comprise:
a first main electrode; a second main electrode, the first main electrode and the second main electrode being electrically connected and are substantially orthogonally arranged to define a first area, a second area, a third area and a fourth area; a plurality of first branch electrodes disposed in the first area; a plurality of second branch electrodes disposed in the second area; a plurality of third branch electrodes disposed in the third area; and a plurality of fourth branch electrodes disposed in the fourth area, wherein the plurality of first branch electrodes, the plurality of second branch electrodes, the plurality of third branch electrodes and the plurality of fourth branch electrodes are electrically connected with one of the first main electrodes and the second main electrodes, the first branch electrodes are arranged parallel to each other, the second branch electrodes are arranged parallel to each other, the third branch electrodes are arranged parallel to each other and the fourth branch electrodes are arranged parallel to each other, and the plurality of first branch electrodes, the plurality of second branch electrodes, the plurality of third branch electrodes and the plurality of fourth branch electrodes respectively extend to different directions from the first main electrode or the second main electrode, the first sub-pixel electrode and the second sub-pixel electrode are mirror symmetry structures with respect to the first slit, the third sub-pixel electrode and the fourth sub-pixel electrode are mirror symmetry structures with respect to the second slit, the first main electrode of the first sub-pixel electrode is substantially parallel to the first slit, the first main electrode of the third sub-pixel electrode is substantially parallel to the second slit.

12 . The pixel array substrate of claim 1 , further comprising:
a plurality of first switches respectively disposed on a side of each of the pixel areas, a first end of each first switch being electrically connected to the respective first pixel electrodes through the first connecting line; and a plurality of second switches respectively disposed on the side of each of the pixel areas, each of the second switches being electrically connected to the second pixel electrode through the second connecting line.

13 . The pixel array substrate of claim 12 , wherein each one of the plurality of pixels further comprises:
a charge-sharing capacitor; and a third switch, wherein a first en

Assignees

• Au Optronics Corp

Inventors

• Wu Ming-Huei
• Tien Kun-Cheng
• Gong Shin-Mei
• Chung Jen-Yang
• Wei Wei-Chun
• Liao Chien-Huang

Classifications

• G02F1/13624

  having more than one switching element per pixel · CPC title

• G02F2201/123

  pixel · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title