Timing window manipulation for noise reduction

Patent metadata

Field	Value
Publication number	US-2017061059-A1
Application number	US-201514836416-A
Country	US
Kind code	A1
Filing date	Aug 26, 2015
Priority date	Aug 26, 2015
Publication date	Mar 2, 2017
Grant date	—

Abstract

Timing window manipulation for noise reduction includes: selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

First claim

1 - 10 . (canceled)

11 . An apparatus for timing window manipulation for noise reduction in a circuit design, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of:
selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

12 . The apparatus of claim 11 , wherein the timing analysis comprises an analysis of a coupled noise effect associated with the victim window.

13 . The apparatus of claim 11 , wherein modifying circuit characteristics of the circuit design with the switching window comprises an action selected from the group consisting of: powering down a circuit, powering up a circuit, changing a wiring path, changing a circuit placement, changing a circuit voltage level, or changing a circuit topology.

14 . The apparatus of claim 11 , wherein the victim window value is based at least on a statistical timing value.

15 . The apparatus of claim 14 , wherein the statistical timing value comprises an arrival time level value.

16 . The apparatus of claim 11 , wherein modifying circuit characteristics of the circuit design within the switching window is performed during an optimization process selected from the group consisting of: a late mode timing closure, an early mode timing closure, or a false switching reduction.

17 . A computer program product for timing window manipulation for noise reduction in a circuit design, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions capable, when executed, of causing a computer to carry out the steps of:
selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

18 . The computer program product of claim 17 , wherein the timing analysis comprises an analysis of a coupled noise effect associated with the victim window.

19 . The computer program product of claim 17 , wherein modifying circuit characteristics of the circuit design with the switching window comprises an action selected from the group consisting of: powering down a circuit, powering up a circuit, changing a wiring path, changing a circuit placement, changing a circuit voltage level, or changing a circuit topology.

20 . The computer program product of claim 17 , wherein the victim window value is based at least on a statistical timing value.

Assignees

• IBM

Inventors

• Gregerson James C
• Kalafala Kerim
• Ko Tsz-Mei
• Schaeffer Gregory M

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077

  Physics · mapped topic