Test apparatus

Patent metadata

Field	Value
Publication number	US-2017045564-A1
Application number	US-201514825425-A
Country	US
Kind code	A1
Filing date	Aug 13, 2015
Priority date	Aug 13, 2015
Publication date	Feb 16, 2017
Grant date	—

Abstract

A reception circuit receives, via a cable, a transmission signal S TX generated by a DUT. A comparator circuit compares a reception signal S RX after signal transmission with at least one threshold signal V TH , and generates a judgment value D OUT that represents a comparison result for every sampling timing. A threshold generation circuit generates at least one threshold signal V TH . A threshold control circuit adjusts each level of at least one threshold signal V TH at a given sampling timing based on the history of the judgment value D OUT acquired at a past sampling timing.

First claim

What is claimed is:

1 . A test apparatus that receives, via a transmission path, a transmission signal generated by a device under test, the test apparatus comprising:
a comparator circuit that compares a reception signal after signal transmission with at least one threshold signal, and generates a judgment value that represents a comparison result for every sampling timing; a threshold generation circuit that generates the at least one threshold signal; and a threshold control circuit that adjusts a level of each of the at least one threshold signal at a given sampling timing based on a history of the judgment value obtained at a past sampling timing.

2 . The test apparatus according to claim 1 , wherein the transmission signal is configured as a binary signal that can switch between a high level and a low level,
wherein the at least one threshold signal includes a single threshold signal, wherein the threshold generation circuit is capable of switching the single threshold signal between a lower level and an upper level that is higher than the lower level according to a control operation by the threshold control circuit, wherein, when the judgment value obtained at an immediately previous sampling timing represents a low level, the threshold control circuit sets the threshold signal to the lower level, and wherein, when the judgment value obtained at an immediately previous sampling timing represents a high level, the threshold control circuit sets the threshold signal to the upper level.

3 . The test apparatus according to claim 1 , wherein the transmission signal is configured as a binary signal that can switch between a high level and a low level,
wherein the at least one threshold signal includes a single threshold signal, wherein the threshold generation circuit is capable of switching the single threshold signal between a plurality of levels according to a control operation by the threshold control circuit, and wherein the threshold control circuit sets the threshold signal to one among the plurality of levels according to a combination of the judgment values acquired at N (N represents an integer) immediately previous timings.

4 . The test apparatus according to claim 3 , wherein the threshold generation circuit is capable of switching the single threshold signal between 2 N levels.

5 . The test apparatus according to claim 1 , further comprising an optimization circuit that optimizes a plurality of levels that can be set for each of the at least one threshold signal in a state in which a training pattern is supplied to the test apparatus via the transmission path instead of the transmission signal generated by the device under test.

6 . The test apparatus according to claim 5 , wherein the optimization circuit optimizes the plurality of levels that can be set for each of the at least one threshold signal such that a bit error rate becomes small.

7 . A test apparatus that receives, via a transmission path, a transmission signal generated by a device under test, the test apparatus comprising:
a comparator circuit that compares a reception signal after signal transmission with at least one threshold signal, and that generates a judgment value that represents a comparison result for every sampling timing; a threshold generation circuit that generates the at least one threshold signal; and an optimization circuit that optimizes a level of the at least one threshold signal in a state in which a training pattern is supplied to the test apparatus via the transmission path instead of the transmission signal generated by the device under test.

Assignees

• Advantest Corp

Inventors

• Kusaka Takashi
• Ishida Masahiro

Classifications

• G11C29/56012

  Timing aspects, clock generation, synchronisation · CPC title

• G11C29/56008

  Error analysis, representation of errors · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G01R31/3171 Primary

  BER [Bit Error Rate] test · CPC title

• G01R27/28 Primary

  Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response (in line transmission systems H04B3/46) · CPC title