Determining worst-case bit patterns based upon data-dependent jitter

Patent metadata

Field	Value
Publication number	US-9435840-B2
Application number	US-201414149806-A
Country	US
Kind code	B2
Filing date	Jan 7, 2014
Priority date	Jan 7, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.

First claim

What is claimed is:

1. A method comprising:
measuring data-dependent jitter capable of being introduced to a channel by a transmitter of the channel, and measuring, by a receiver of the channel, a step response associated with the channel generated in response to a bit transition by the transmitter;
deriving, by a computing system, a sequence pattern for input into the channel based, at least in part, on the data-dependent jitter and the step response associated with the channel; and
determining, by the computing system, a bit error rate for the channel based, at least in part, on the sequence pattern.

2. The method of claim 1 , wherein deriving the sequence pattern further comprises:
preparing a structure of connected elements;
determining paths through the connected elements in the structure based, at least in part, on jitter samples associated with the data-dependent jitter; and
building the sequence pattern based on the paths through the connected elements.

3. The method of claim 2 , wherein deriving the sequence pattern further comprises building an indexed table of the jitter samples, wherein the structure of the connected elements is prepared based on the indexed table of the jitter samples.

4. The method of claim 1 , further comprising generating, by the computing system, an eye diagram corresponding to signals capable of being transmitted over the channel in response to the sequence pattern and received at the receiver.

5. The method of claim 4 , wherein the sequence pattern is a worst-case bit pattern when the eye diagram has a minimal eye opening.

6. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
identifying a measurement of data-dependent jitter capable of being introduced to a channel by a transmitter of the channel, and identifying a step response associated with the channel measured by a receiver of the channel, wherein the step response is generated in response to a bit transition by the transmitter;
deriving a sequence pattern for input into the channel based, at least in part, on the data-dependent jitter and the step response associated with the channel; and
determining a bit error rate for the channel based, at least in part, on the sequence pattern.

7. The apparatus of claim 6 , wherein deriving the sequence pattern further comprises:
preparing a structure of connected elements;
determining paths through the connected elements in the structure based, at least in part, on jitter samples associated with the data-dependent jitter; and
building the sequence pattern based on the paths through the connected elements.

8. The apparatus of claim 7 , wherein deriving the sequence pattern further comprises building an indexed table of the jitter samples, wherein the structure of the connected elements is prepared based on the indexed table of the jitter samples.

9. The apparatus of claim 6 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising generating an eye diagram corresponding to signals capable of being transmitted over the channel in response to the sequence pattern and received at the receiver.

10. The apparatus of claim 9 , wherein the sequence pattern is a worst-case bit pattern when the eye diagram has a minimal eye opening.

11. A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
identify a measurement of data-dependent jitter capable of being introduced to a channel by a transmitter of the channel;
identify a step response associated with the channel measured by a receiver of the channel, wherein the step response is generated in response to a bit transition by the transmitter;
derive a sequence pattern for input into the channel based, at least in part, on the data-dependent jitter and the step response associated with the channel; and
determine a bit error rate for the channel based, at least in part, on the sequence pattern.

12. The system of claim 11 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to:
prepare a structure of connected elements;
determine paths through the connected elements in the structure based, at least in part, on jitter samples associated with the data-dependent jitter; and
build the sequence pattern based on the paths through the connected elements.

13. The system of claim 12 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to build an indexed table of the jitter samples, wherein the structure of the connected elements is prepared based on the indexed table of the jitter samples.

14. The system of claim 11 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to generate an eye diagram corresponding to signals capable of being transmitted over the channel in response to the sequence pattern and received at the receiver.

15. The system of claim 14 , wherein the sequence pattern is a worst-case bit pattern when the eye diagram has a minimal eye opening.

Assignees

• Mentor Graphics Corp

Inventors

• Dmitriev-Zdorov Vladimir

Classifications

• G01R31/00 Primary

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G01R31/3171 Primary

  BER [Bit Error Rate] test · CPC title

• G01R31/31709

  Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901) · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L1/203

  Details of error rate determination, e.g. BER, FER or WER · CPC title