Via structure and circuit board having the via structure

Patent metadata

Field	Value
Publication number	US-2017018490-A1
Application number	US-201615152682-A
Country	US
Kind code	A1
Filing date	May 12, 2016
Priority date	Jul 16, 2015
Publication date	Jan 19, 2017
Grant date	—

Abstract

The present disclosure provides a via structure and a multilayer circuit board including the via structure. The via structure is provided in three or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and including at least one current input layer and at least one current output layer; wherein the via structure includes a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, and a part of the rows of vias puncture through all of the conductor layers, and the other part of the rows of vias puncture through a part of the conductor layers. By using the via structure in the present disclosure, the vias are subject to even temperature and thus the lifetime of the circuit board is extended.

First claim

What is claimed is:

1 . A via structure, provided in three or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and comprising at least one current input layer and at least one current output layer;
wherein the via structure comprises a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, and a part of the rows of vias puncture through all of the conductor layers, and the other part of the rows of vias puncture through a part of the conductor layers.

2 . The via structure according to claim 1 , wherein the plurality of rows of vias are divided into a plurality of groups, vias in the same group puncture through the same current input layer and the same current output layer, and each group of vias comprise at least one row of vias.

3 . The via structure according to claim 2 , wherein each group of vias are provided at an edge of one of at least one overlapping region of downward projections for the at least one current input layer and the at least one current output layer.

4 . The via structure according to claim 2 , wherein tangential directions of imaginary curved lines formed by linearly fitting positions of respective rows of vias are perpendicular to a flowing direction along which current flows through the conductor layers.

5 . The via structure according to claim 2 , wherein the numbers of vias in rows close to interior of the overlapping region are decreased as compared with the numbers of vias in rows close to the edges of the overlapping region.

6 . The via structure according to claim 2 , wherein, among the groups of vias, the number of vias in one group connecting a plurality of conductor layers rises with increasing of an in-out ratio which is defined as N/M if N≧M, or M/N if N≦M, wherein N is the number of conductor layers from which the current flows into the one group of vias, and M is the number of conductor layers which the current from the via structure flows to.

7 . The via structure according to claim 2 , wherein a distance between at least two adjacent rows in a group is smaller than a size of a via.

8 . The via structure according to claim 1 , wherein a distance between at least two adjacent rows of vias is smaller than or equal to a size of a via.

9 . The via structure according to claim 1 , wherein tangential directions of imaginary curved lines formed by linearly fitting positions of respective rows of vias are perpendicular to a flowing direction along which current flows through the conductor layers.

10 . A via structure, provided in two or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and comprising at least one current input layer and at least one current output layer;
wherein the via structure comprises a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, an in-out ratio of each row of vias is (A+1)/A, where A is an positive integer.

11 . The via structure according to claim 10 , wherein when the number of conductor layers from which current flows into one row of vias is M, the number of conductor layers which the current from the row of vias flows to is N, the in-out ratio is defined as N/M if N≧M, or M/N if N≦M.

12 . The via structure according to claim 10 , wherein the plurality of rows of vias are divided into a plurality of groups, vias in the same group puncture through the same current input layer and the same current output layer, and each group of vias comprise at least one row of vias.

13 . The via structure according to claim 12 , wherein each group of vias are provided at an edge of one of at least one overlapping region of downward projections for the at least one current input layer and the at least one current output layer.

14 . The via structure according to claim 12 , wherein tangential directions of imaginary curved lines formed by linearly fitting positions of respective rows of vias are perpendicular to a flowing direction along which current flows through the conductor layers.

15 . The via structure according to claim 12 , wherein the numbers of vias in rows close to interior of the overlapping region are decreased as compared with the numbers of vias in rows close to the edge of the overlapping region.

16 . The via structure according to claim 12 , wherein a distance between at least two adjacent rows in a group is smaller than a size of a size.

17 . The via structure according to claim 10 , wherein a distance between at least two adjacent rows of vias is smaller than or equal to a size of a via.

18 . The via structure according to claim 10 , wherein tangential directions of imaginary curved lines formed by linearly fitting positions of respective rows of vias are perpendicular to a flowing direction along which current flows through the conductor layers.

19 . A multilayer circuit board, comprising a via structure provided in three or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and comprising at least one current input layer and at least one current output layer;
wherein the via structure comprises a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, and a part of the rows of vias puncture through all of the conductor layers, and the other part of the rows of vias puncture through a part of the conductor layers.

20 . A multilayer circuit board, comprising a via structure provided in two or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and comprising at least one current input layer and at least one current output layer;
wherein the via structure comprises a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, an in-out ratio of each row of vias is (A+1)/A, where A is an positive integer.

Assignees

• Delta Electronics Shanghai Co

Inventors

• Li Yuechao
• Feng Weiyi
• Zhang Weiqiang
• Wu Hongyang
• Zhou Ziying

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H01L23/49822

  Electricity · mapped topic

• H01L23/49827 Primary

  Electricity · mapped topic

• H01L23/49838

  Electricity · mapped topic