Semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017012003-A1
Application number	US-201615275853-A
Country	US
Kind code	A1
Filing date	Sep 26, 2016
Priority date	Sep 30, 2011
Publication date	Jan 12, 2017
Grant date	—

Abstract

There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate having a ground electrode formed on one surface thereof; at least one electronic component mounted on one surface of the substrate; an insulation layer including an exposed part exposing the ground electrode and a cover part covering the electronic component; and a shielding layer electrically connected to the ground electrode and covering the insulation layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor package, the method comprising:
preparing a substrate having a ground electrode formed on one surface thereof and at least one electronic component formed on one surface of the substrate; stacking and compressing an insulation material to cover the substrate; forming an insulation layer including an exposed part exposing the ground electrode by removing a portion of the insulation material and a cover part covering the electronic component; and forming a shielding layer by applying a conductive material to the insulation layer.

2 . The method of claim 1 , wherein the forming of the shielding layer is undertaken by applying the conductive material in a spray coating scheme.

3 . The method of claim 1 , wherein the exposed part is formed by removing the portion of the insulation material using a laser beam.

4 . The method of claim 1 , wherein the insulation material is insulation tape.

5 . The method of claim 1 , wherein the stacking and compressing of the insulation material includes:
attaching the insulation material to the substrate; and rolling or pressing the insulation material.

6 . The method of claim 1 , wherein the exposed part has a dotted line or a solid line shape.

7 . The method of claim 1 , wherein the substrate includes at least one shielding area, and
the exposed part encloses the shielding area.

8 . A method of manufacturing a semiconductor package, the method comprising:
preparing a substrate having a ground electrode formed on one surface thereof and at least one electronic component formed on one surface of the substrate; and attaching composite tape to the substrate, the composite tape including a shielding layer formed of a conductive material and an insulation layer formed on the shielding layer and including an exposed part exposing a portion of the shielding layer to thereby electrically connect the shielding layer to the ground electrode and a cover part covering the electronic component.

9 . The method of claim 8 , further comprising rolling or pressing a surface of the composite tape attached to the substrate.

10 . The method of claim 8 , wherein the exposed part has a dotted line or a solid line shape.

11 . The method of claim 8 , wherein the substrate includes at least one shielding area, and
the exposed part encloses the shielding area.

Assignees

• Samsung Electro Mech

Inventors

• Yoo Jin O

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/124

  the encapsulations having cavities other than that occupied by chips · CPC title