Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017011925-A1
Application number	US-201514795751-A
Country	US
Kind code	A1
Filing date	Jul 9, 2015
Priority date	Jul 9, 2015
Publication date	Jan 12, 2017
Grant date	—

Abstract

A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

First claim

1 - 10 . (canceled)

11 . A semiconductor structure, comprising:
an isolation structure formed in a semiconductor substrate and electrically isolating device regions of the semiconductor substrate; a gate stack located on the isolation structure, wherein the gate stack comprises a first portion in contact with the isolation structure, and a second portion extending from the first portion into at least one of the device regions; a spacer formed along a sidewall of the gate stack on the isolation structure; and a patterned resist protective oxide located on the isolation structure and covering a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

12 . The semiconductor structure according to claim 11 , wherein the isolation structure has a recess formed on a top portion of the isolation structure, and the recess has a bottom surface extending on a level below a principal surface of the semi conductor substrate.

13 . The semiconductor structure according to claim 12 , wherein the patterned resist protective oxide comprises a horizontal portion in contact with the bottom surface of the recess, and a vertical portion extending from the horizontal portion to the sidewall of the spacer.

14 . The semiconductor structure according to claim 13 , further comprising a contact etching stop layer on the patterned resist protective oxide, wherein the contact etching stop layer has a horizontal part and a vertical part respectively in contact with the horizontal portion and the vertical portion of the patterned resist protective oxide.

15 . The semiconductor structure according to claim 14 , wherein the horizontal part of the contact etching stop layer extends on a level below the principal surface of the semiconductor substrate.

16 . (canceled)

17 . The semiconductor structure according to claim 11 , wherein the isolation structure comprises a shallow trench isolation structure.

18 . The semiconductor structure according to claim 11 , wherein the gate stack comprises a gate electrode, a high-k dielectric, and a protective layer interposed between the gate electrode and the high-k dielectric.

19 . The semiconductor structure according to claim 11 , wherein the spacer comprises a main spacer wall and a seal interposed between the main spacer wall and the gate stack.

20 . A semiconductor structure, comprising:
a shallow trench isolation structure formed in a semiconductor substrate and electrically isolating device regions of the semiconductor substrate; a gate stack located on and in contact with the isolation structure; a spacer formed along a sidewall of the gate stack; a patterned resist protective oxide located on the isolation structure and covering a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack, wherein the patterned resist protective oxide comprises:
a horizontal portion in contact with the shallow trench isolation structure; and
a vertical portion extending from the horizontal portion to the sidewall of the spacer; and
a contact etching stop layer on the patterned resist protective oxide, wherein the contact etching stop layer has a horizontal part and a vertical part respectively in contact with the horizontal portion and the vertical portion of the patterned resist protective oxide.

21 . The semiconductor structure according to claim 20 , wherein the patterned resist protective oxide has a thickness of about 5 nm to about 50 nm.

22 . The semiconductor structure according to claim 20 , wherein the isolation structure has a recess on a top portion of the isolation structure, and the recess has a bottom surface extending on a level below a principal surface of the semi conductor substrate.

23 . The semiconductor structure according to claim 22 , wherein the horizontal portion of the patterned resist protective oxide is located on the bottom surface of the recess, and a top surface of the horizontal portion extends on a level below the principal surface of the semiconductor substrate.

24 . The semiconductor structure according to claim 22 , wherein the horizontal part of the contact etching stop layer is located in the recess.

25 . The semiconductor structure according to claim 23 , wherein a top surface of the horizontal part of the contact etching stop layer extends on a level below the principal surface of the semiconductor substrate.

26 . The semiconductor structure according to claim 25 , wherein a distance between the principal surface and the top surface of the horizontal part is about 2 nm to about 50 nm.

27 . The semiconductor structure according to claim 20 , wherein the gate stack comprises a metal gate, a high-k dielectric, and a protective layer interposed between the metal gate and the high-k dielectric.

28 . The semiconductor structure according to claim 20 , wherein the spacer comprises a main spacer wall and a seal interposed between the main spacer wall and the gate stack.

29 . A semiconductor structure, comprising:
an isolation structure formed in a semiconductor substrate and electrically isolating device regions of the semiconductor substrate; a gate stack extending from one of the device regions to the isolation structure; a spacer formed along a sidewall of the gate stack on the isolation structure, wherein the spacer is in contact with the isolation structure; and a patterned resist protective oxide located on the isolation structure and extending from the isolation structure to a sidewall of the spacer such that an interface between the spacer and the isolation structure is covered by the patterned resist protective oxide.

30 . The semiconductor structure according to claim 29 , wherein the patterned resist protective oxide covers an entirety of the isolation structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Chen-Liang
• Liang Chia-Yao
• Chen Jui-Long
• Lin Sheng-Yuan
• Huang Yi-Lii
• LEE Kuo-Hsi
• Chen Po-An

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/414

  of metal-silicide materials · CPC title