Multilayer ceramic electronic component

US2017011850A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017011850-A1
Application numberUS-201615071821-A
CountryUS
Kind codeA1
Filing dateMar 16, 2016
Priority dateJul 6, 2015
Publication dateJan 12, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer ceramic electronic component includes a ceramic body in which dielectric layers and internal electrodes are alternately disposed. Ceramic-metal compound layers are disposed on interfaces between the internal electrodes and the dielectric layers. Additionally, in some examples, spaces between adjacent internal electrodes are fully occupied by the dielectric layers and the dielectric layers contain a ceramic-metal compound containing metal particle. The ceramic-metal compound layer may have an embossing type configuration or a dendrite type configuration.

First claim

Opening claim text (preview).

What is claimed is: 1 . A multilayer ceramic electronic component comprising: a ceramic body in which dielectric layers and internal electrodes are alternately disposed, wherein ceramic-metal compound layers are disposed on interfaces between the internal electrodes and the dielectric layers. 2 . The multilayer ceramic electronic component of claim 1 , wherein the ceramic-metal compound layer has an embossing type configuration. 3 . The multilayer ceramic electronic component of claim 1 , wherein the ceramic-metal compound layer has a dendrite type configuration. 4 . The multilayer ceramic electronic component of claim 1 , wherein the ceramic-metal compound layer contains 5 to 30 vol % of a metal. 5 . The multilayer ceramic electronic component of claim 1 , wherein a metal of the ceramic-metal compound layer has a particle size of 5 nm to 600 nm. 6 . The multilayer ceramic electronic component of claim 1 , wherein a ratio (Td/Tt) satisfies Td/Tt>0.5, wherein Tt corresponds to a thickness Tt of one of the dielectric layers including a thickness of the ceramic-metal compound layers and Td corresponds to a thickness Td of the portion of the one dielectric layer exclusive of the ceramic-metal compound layers. 7 . The multilayer ceramic electronic component of claim 1 , wherein a metal of the ceramic-metal compound layer has Fermi energy of 4.0 eV to 6.0 eV. 8 . A multilayer ceramic electronic component comprising: a ceramic body in which dielectric layers and internal electrodes are alternately disposed, wherein spaces between adjacent internal electrodes are fully occupied by the dielectric layers containing a ceramic-metal compound containing metal particles, and by ceramic-metal compound layers disposed on interfaces between the internal electrodes and the dielectric layers, and wherein metal nano-particles are disposed in central portions of the dielectric layers. 9 . The multilayer ceramic electronic component of claim 8 , wherein the ceramic-metal compound layer has an embossing type configuration. 10 . The multilayer ceramic electronic component of claim 8 , wherein the ceramic-metal compound layer has a dendrite type configuration. 11 . The multilayer ceramic electronic component of claim 8 , wherein the ceramic-metal compound contains 5 to 30 vol % of a metal. 12 . The multilayer ceramic electronic component of claim 8 , wherein a metal of the ceramic-metal compound has a particle size of 5 nm to 600 nm. 13 . The multilayer ceramic electronic component of claim 8 , wherein a ratio (Td/Tt) satisfies Td/Tt>0.5, wherein Tt corresponds to a thickness Tt of one of the dielectric layers including a thickness of the ceramic-metal compound layers and Td corresponds to a thickness Td of the portion of the one dielectric layer exclusive of the ceramic-metal compound layers. 14 . The multilayer ceramic electronic component of claim 8 , wherein a metal of the ceramic-metal compound has Fermi energy of 4.0 eV to 6.0 eV. 15 . A multilayer ceramic electronic component comprising: a plurality of internal electrodes disposed parallel to each other and spaced apart from each other within the multilayer ceramic electronic component, wherein the internal electrodes each have ceramic-metal compound layers disposed on two opposing surfaces thereof. 16 . The multilayer ceramic electronic component of claim 15 , further comprising: dielectric layers disposed between pairs of adjacent internal electrodes of the plurality of internal electrodes; and two external electrodes disposed on respective opposing end surfaces of a ceramic body including the dielectric layers and the internal electrodes. 17 . The multilayer ceramic electronic component of claim 16 , wherein the dielectric layers disposed between the pairs of adjacent internal electrodes include a ceramic-metal compound containing metal particles. 18 . The multilayer ceramic electronic component of claim 17 , wherein spaces between the pairs of adjacent internal electrodes are exclusively filled with the dielectric layers including the ceramic-metal compound containing metal particles and with the ceramic-metal compound layers disposed on surfaces of the internal electrodes. 19 . The multilayer ceramic electronic component of claim 18 , wherein the ceramic-metal compound layers have an embossing type configuration. 20 . The multilayer ceramic electronic component of claim 18 , wherein the ceramic-metal compound layers have a dendrite type configuration.

Assignees

Inventors

Classifications

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title

  • Form of non-self-supporting electrodes · CPC title

  • H01G4/08Primary

    Inorganic dielectrics · CPC title

  • Fried electrodes · CPC title

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What does patent US2017011850A1 cover?
A multilayer ceramic electronic component includes a ceramic body in which dielectric layers and internal electrodes are alternately disposed. Ceramic-metal compound layers are disposed on interfaces between the internal electrodes and the dielectric layers. Additionally, in some examples, spaces between adjacent internal electrodes are fully occupied by the dielectric layers and the dielectric…
Who is the assignee on this patent?
Samsung Electro Mech
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).