Method and apparatus for verifying integrity in memory-disaggregated environment
US-12153525-B2 · Nov 26, 2024 · US
Dynamically Controlling Cache Size To Maximize Energy Efficiency
US2017010656A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017010656-A1 |
| Application number | US-201615270208-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 20, 2016 |
| Priority date | Oct 31, 2011 |
| Publication date | Jan 12, 2017 |
| Grant date | — |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
First claim
Opening claim text (preview).
What is claimed is: 1 . A processor comprising: a first domain including a plurality of cores to independently execute instructions; a second domain including at least one graphics engine; a cache memory coupled to the plurality of cores and including a plurality of partitions; and a power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state.
Assignees
Inventors
Classifications
using adaptive policy · CPC title
by switching off individual functional units in the computer system · CPC title
- G06F12/0864Primary
using pseudo-associative means, e.g. set-associative or hashing · CPC title
Partitioned cache · CPC title
Power efficiency · CPC title
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Frequently asked questions
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- What does patent US2017010656A1 cover?
- In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0864. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jan 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).