Silicon germanium alloy fins with reduced defects

Patent metadata

Field	Value
Publication number	US-2016322501-A1
Application number	US-201514699491-A
Country	US
Kind code	A1
Filing date	Apr 29, 2015
Priority date	Apr 29, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure, said method comprising:
forming a silicon germanium alloy portion on each sidewall surface of a silicon fin, said silicon fin extending upward from a remaining portion of a silicon substrate; providing a trench isolation dielectric material on exposed surfaces of said remaining portion of said silicon substrate and on exposed sidewall surfaces of each silicon germanium alloy portion and said silicon fin; and converting a portion of the silicon fin that is located laterally adjacent each silicon germanium alloy portion into a silicon germanium alloy fin, wherein said silicon germanium alloy fin comprises a wide upper portion and a narrower lower portion, wherein said silicon germanium alloy fin has a vertically graded germanium content in which said wide upper portion of said silicon germanium alloy fin has a greater germanium content than said narrower lower portion of said silicon germanium alloy fin and wherein sidewall surfaces of said narrower lower portion of said silicon germanium alloy fin are vertically coincident with sidewall surfaces of said silicon fin portion.

2 . The method of claim 1 , wherein said converting comprises an oxidation process or a thermal anneal in an inert ambient.

3 . The method of claim 1 , wherein said forming said silicon germanium alloy portion comprises:
epitaxially growing a silicon germanium alloy layer on exposed surfaces of said silicon fin; forming a sacrificial dielectric structure having a topmost surface that is located beneath a topmost surface of said silicon fin; forming a sacrificial spacer on a sidewall surface of said silicon germanium alloy layer not protected by said sacrificial dielectric structure; removing said sacrificial dielectric structure; removing portions of said silicon germanium alloy layer not protected by said sacrificial spacer to provide each silicon germanium alloy portion; and removing said sacrificial spacer.

4 . The method of claim 3 , wherein said silicon fin comprises a hard mask cap, said hard mask cap is formed prior to forming said silicon germanium alloy layer.

5 . The method of claim 1 , further comprising recessing said trench isolation dielectric material to expose a portion of said wide upper portion of the silicon germanium alloy fin and to provide a trench isolation structure.

6 . The method of claim 6 , further comprising a functional gate structure straddling said exposed portion of said wide upper portion of said silicon germanium alloy fin.

7 . A method of forming a semiconductor structure, said method comprising:
forming a silicon germanium alloy layer on each sidewall surface of a silicon fin, said reduced silicon fin extending upward from a silicon pedestal portion which is present on a silicon base substrate; providing a trench isolation dielectric material on exposed surfaces of said silicon base substrate and on exposed sidewall surfaces of each silicon germanium layer and said silicon fin; and converting a portion of the silicon fin that is located laterally adjacent each silicon germanium layer into a silicon germanium alloy fin, wherein said silicon germanium alloy fin comprises a narrow upper portion and a wider lower portion, wherein said silicon germanium alloy fin has a vertically graded germanium content in which said narrow upper portion of said silicon germanium alloy fin has a greater germanium content than said wider lower portion of said silicon germanium alloy fin and wherein sidewall surfaces of said wider lower portion of said silicon germanium alloy fin are vertically coincident with sidewall surfaces of said silicon pedestal portion.

8 . The method of claim 7 , wherein said converting comprises an oxidation process or a thermal anneal in an inert ambient.

9 . The method of claim 7 , wherein said forming said silicon germanium alloy layer comprises
providing an initial silicon fin having a first width, said initial silicon fin is capped with a hard mask material; thinning said initial silicon fin to provide said silicon fin, said silicon fin having a second width that is less than the first width; and epitaxially growing said silicon germanium alloy layer.

10 . The method of claim 9 , further comprising:
forming a dielectric spacer on exposed surfaces of said silicon germanium alloy layer; and recessing exposed portion of a remaining portion of a silicon substrate to provide said silicon pedestal portion present on said silicon base substrate.

11 . The method of claim 7 , further comprising recessing said trench isolation dielectric material to expose a portion of said narrow upper portion of the silicon germanium alloy fin and to provide a trench isolation structure.

12 . The method of claim 11 , further comprising a functional gate structure straddling said exposed portion of said narrow upper portion of said silicon germanium alloy fin.

13 . A semiconductor structure comprising:
a silicon fin portion extending upward from a remaining portion of a silicon substrate; and a silicon germanium alloy fin located on said silicon fin portion and comprising a wide upper portion and a narrower lower portion, wherein said silicon germanium alloy fin has a vertically graded germanium content in which said wide upper portion of said silicon germanium alloy fin has a greater germanium content than said narrower lower portion of said silicon germanium alloy fin and wherein sidewall surfaces of said narrower lower portion of said silicon germanium alloy fin are vertically coincident with sidewall surfaces of said silicon fin portion.

14 . The semiconductor structure of claim 13 , further comprising a silicon oxide portion located on said vertical sidewalls of said narrower lower portion of said silicon germanium alloy fin and sidewall surfaces of said silicon fin portion.

15 . The semiconductor structure of claim 13 , further comprising a trench isolation structure located on exposed surfaces of said remaining portion of said silicon substrate and adjacent said silicon germanium alloy fin.

16 . The semiconductor structure of claim 13 , further comprising a functional gate structure straddling said wide upper portion of said silicon germanium alloy fin.

17 . A semiconductor structure comprising:
a silicon pedestal portion extending upward from a silicon base substrate; and a silicon germanium alloy fin located on said silicon pedestal portion and comprising a narrow upper portion and a wider lower portion, wherein said silicon germanium alloy fin has a vertically graded germanium content in which said narrow upper portion of said silicon germanium alloy fin has a greater germanium content than said wider lower portion of said silicon germanium alloy fin and wherein sidewall surfaces of said wider lower portion of said silicon germanium alloy fin are vertically coincident with sidewall surfaces of said silicon pedestal portion.

18 . The semiconductor structure of claim 17 , further comprising a silicon oxide portion located on said vertical sidewalls of said wider lower portion of said silicon germanium alloy fin and sidewall surfaces of said silicon pedestal portion.

19 . The semiconductor structure of claim 17 , further comprising a trench isolation structure located on exposed surfaces of said remaining portion of said silicon substrate and adjacent said silicon germanium alloy fin.

20 . The semiconductor structure of claim 17 , further comprising a functional gate structure straddling said n

Assignees

• IBM

Inventors

• Cheng Kangguo
• He Hong
• Li Juntao

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P36/03

  within silicon bodies · CPC title

• H10P36/00

  Gettering within semiconductor bodies · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2925

  Surface structures · CPC title