Display device

Patent metadata

Field	Value
Publication number	US-2016379907-A1
Application number	US-201615190081-A
Country	US
Kind code	A1
Filing date	Jun 22, 2016
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.

First claim

What is claimed is:

1 . A display device comprising:
a display area configured to display an image; a peripheral area neighboring the display area; at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT; and first to third dummy circuits separated from the test TFT, wherein each of the first to third dummy circuits includes a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.

2 . The display device of claim 1 , wherein at least one of the first to third dummy circuits overlaps at least a portion of at least one of the test pads in the depth dimension of the display device.

3 . The display device of claim 1 , wherein the test TFT includes:
a test semiconductor layer including a source region and a drain region; a test gate electrode overlapping the test semiconductor layer in the depth dimension of the display device; and a test source electrode and a drain electrode respectively connected to the source and drain regions of the test semiconductor layer.

4 . The display device of claim 3 , wherein the test pads include:
a first test pad electrically connected to the test source electrode; a second test pad electrically connected to the test drain electrode; and a third test pad electrically connected to the test gate electrode.

5 . The display device of claim 4 , further comprising:
a first connector configured to electrically connect the test source electrode to the first test pad; and a second connector configured to electrically connect the test drain electrode to the second test pad.

6 . The display device of claim 5 , wherein the first to third dummy circuits respectively overlap the first to third test pads in the depth dimension of the display device.

7 . The display device of claim 6 , wherein the first dummy circuit overlaps the second connector in the depth dimension of the display device.

8 . The display device of claim 6 , further comprising:
a first insulating layer interposed between the first dummy semiconductor layer and the first dummy gate electrode; and a second insulating layer interposed between the first dummy gate electrode and the first to third test pads, wherein the first insulating layer has a first contact hole formed over the first dummy semiconductor layer, and wherein the second insulating layer has a second contact hole formed over the first dummy gate electrode.

9 . The display device of claim 5 , wherein the first connector and the test source electrode are integrally formed, and wherein the second connector and the test drain electrode are integrally formed.

10 . The display device of claim 9 , wherein the first connector and the first test pad are integrally formed, and wherein the second connector and the second test pad are integrally formed.

11 . The display device of claim 3 , wherein the distance between at least one of the first to third dummy circuits and the test semiconductor layer is in the range of about 50 μm to about 100 μm.

12 . The display device of claim 1 , wherein the at least one TEG includes a plurality of TEGs, and wherein the display device further comprises a fourth dummy circuit formed between neighboring TEGs.

13 . The display device of claim 12 , wherein the fourth dummy circuit includes a plurality of second dummy semiconductor layers and a plurality of second dummy gate electrodes overlapping at least a portion of one of the second dummy semiconductor layers in the depth dimension of the display device.

14 . A display device comprising:
a substrate including a display area and a non-display area formed adjacent to the display area; a pixel formed in the display area and including a display thin film transistor (TFT), wherein the display TFT includes a display semiconductor layer; and a first dummy circuit formed in the non-display area, wherein the first dummy circuit includes a first dummy semiconductor layer and a first dummy gate electrode overlapping at least a portion of the first dummy semiconductor layer in the depth dimension of the display device, and wherein the display semiconductor layer and the first dummy semiconductor layer have substantially the same shape.

15 . The display device of claim 14 , further comprising at least one test element group (TEG) formed in the non-display area and including a test TFT and at least one test pad electrically connected to the test TFT, wherein the test TFT includes the first dummy semiconductor layer.

16 . The display device of claim 15 , wherein the first dummy semiconductor layer is separated from the test pad.

17 . The display device of claim 16 , wherein the test TFT further comprises a test gate electrode configured to electrically connect the first dummy semiconductor layer to the test pad.

18 . The display device of claim 17 , further comprising a second dummy circuit formed adjacent to the first dummy circuit and a third dummy circuit formed adjacent to the second dummy circuit, wherein the test TFT further includes a test source electrode and a test drain electrode, and wherein the test source and drain electrodes are respectively connected to the second and third dummy circuits.

19 . The display device of claim 18 , further comprising a connector configured to electrically connect the drain electrode of the test TFT to the third dummy circuit, wherein the connector does not overlap the second dummy circuit in the depth dimension of the display device.

20 . The display device of claim 19 , wherein the test TFT further comprises:
a gate insulating layer formed over the first dummy semiconductor layer; and an interlayer insulating layer formed over the gate insulating layer and the first dummy gate electrode, wherein the gate and interlayer insulating layers have a first contact hole through which the test pad and the first semiconductor layer are connected, and wherein the interlayer insulating layer has a second contact hole through which the test pad and the first dummy gate electrode are connected.

Assignees

• Samsung Display Co Ltd

Inventors

• Ko Moo Soon
• Lee Jeong-Soo
• Kim Jung Hwa

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title