Method and system for aggregation-friendly address assignment to pcie devices

Patent metadata

Field	Value
Publication number	US-2016378706-A1
Application number	US-201514753400-A
Country	US
Kind code	A1
Filing date	Jun 29, 2015
Priority date	Jun 29, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

First claim

What is claimed is:

1 . A peripheral component interconnect express (PCI-e) system comprising:
a processor operable to perform a method of assigning addresses to nodes of a topology tree of the PCI-e system, comprising: (a) assigning addresses to the PCI-e topology tree, said (a) comprising:
traversing, at a level and in a breadth direction, down-link couplings to an interconnection of the PCI-e system;
ascertaining, at the level, which of the down-link couplings are connected to nodes; and
assigning addresses, at the level, to nodes of ascertained down-link couplings that have nodes;
(b) propagating a level of the PCI-e topology tree, said (b) comprising:
traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e system;
ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction; and
consecutively proceeding, in the depth direction, to a next level of the down-link coupling of a next interconnection; and
(c) alternatively repeating (a) and (b) until the nodes are assigned addresses.

2 . The PCI-e system of claim 1 , wherein (c) results in consecutive address assignment for nodes and wherein the consecutive address assignment prevents gaps in address space.

3 . The PCI-e system of claim 1 , wherein (c) results in a substantially minimal allocation of address space.

4 . The PCI-e system of claim 1 , wherein the interconnection comprises one of a switch and a port for coupling downlinks.

5 . The PCI-e system of claim 1 , wherein the next level comprises one of an upper and a lower level of a next interconnection.

6 . The PCI-e system of claim 1 , wherein the level comprises an initial level of the interconnection coupled to a root connection of the topological tree.

7 . The PCI-e system of claim 1 , further comprising:
a non-transparent bridging (NTB) for additional downlink connections between interconnections of the topology tree.

8 . The PCI-e system of claim 7 , further comprising:
enabling a redundant downlink connection between interconnections of the topology tree by allocating addresses to the NTB downlink connections.

9 . The PCI-e system of claim 7 , wherein the NTB is positioned between a first and a second interconnection and wherein further the first and second interconnections are not previously coupled via downlink couplings.

10 . The PCI-e system of claim 7 , further comprising:
allocating a first set of addresses to a node of a first address in a sub-tree to the first interconnection; allocating a second set of addresses to a node of a second address in a sub-tree to the second interconnection; programming a single address of the first address in a translation register with addresses of a first address and a corresponding first set of addresses of the sub-tree of the first interconnection; programming a single address of the second address in a translation register with addresses of a second address and a corresponding second set of addresses of the sub-tree of the second interconnection; and using the registers, translating addresses of packets arriving on either side of the NTB between the first and second interconnections to either the first or second addresses of the sets of first and second addresses.

11 . A method of assigning addresses and propagating nodes of a peripheral component interconnect express PCI-e system, the method comprising:
assigning addresses at each level of the PCI-e system, the assigning comprising:
traversing, at a given level and in a breadth direction, down-link couplings to an interconnection of the PCI-e system;
determining, at the level, which of the down-link couplings are coupled to nodes; and
assigning addresses, at the level, to nodes of determined down-link couplings having nodes;
propagating each level of the PCI-e system, the propagating comprising:
traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e system;
determining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction; and
consecutively proceeding, in the depth direction, to a next level of the down-link coupling of a next interconnection; and
alternately repeating the assigning and the propagating until the nodes are assigned addresses within the PCI-e system.

12 . The method of claim 11 , wherein the alternately repeating prevents gaps in address space by resulting in consecutive address assignments being assigned for nodes.

13 . The method of claim 11 , wherein the alternately repeating results in a substantially minimal allocation of address space.

14 . The method of claim 11 , wherein the interconnection comprises one of a switch and a port for coupling downlinks.

15 . The method of claim 11 , wherein the next level comprises one of an upper and a lower level of a next interconnection.

16 . The method of claim 11 , wherein the level comprises an initial level of the interconnection coupled to a root connection of the topological tree.

17 . The method claim 14 , wherein the assigning and the propagating performed on nodes commencing at a first level and ending at the first level results in address assignment for tree branches of the topological tree.

18 . In a peripheral component interconnect express (PCI-e) system using non-transparent bridging (NTB) for facilitating extra connections in its topology tree, the NTB performing:
allocating a first set of addresses to a node of a first address in a sub-tree with a first interconnection switch as a root; allocating a second set of addresses to a node of a second address in a sub-tree with a second interconnection switch as a root; programming a single address of the first address in a translation register with addresses of a first address and a corresponding first set of addresses of the sub-tree of the first interconnection; programming a single address of the second address in a translation register with addresses of a second address and a corresponding second set of addresses of the sub-tree of the second interconnection; and using the registers, translating addresses of packets arriving on either side of the NTB between the first and second interconnections to either the first or second addresses of the sets of first and second addresses.

19 . The NTB of claim 18 , further performing:
enabling a redundant downlink connection between interconnections of the topology tree by allocating sets of addresses to NTB downlink connections.

20 . The NTB of claim 18 wherein the NTB comprises sets of addresses of substantially minimal length.

21 . The NTB of claim 18 , wherein the first and the second interconnections comprise one of switches and ports for coupling downlinks.

Assignees

• Futurewei Technologies Inc

Inventors

• Egi Norbert
• Boyle Thomas
• Shi Guangyu

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• G06F2213/0026

  PCI express · CPC title