Method and apparatus for offloading functional data from an interconnect component

Patent metadata

Field	Value
Publication number	US-2016110275-A1
Application number	US-201314897671-A
Country	US
Kind code	A1
Filing date	Jun 18, 2013
Priority date	Jun 18, 2013
Publication date	Apr 21, 2016
Grant date	—

Abstract

An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

First claim

1 . An interconnect offload component arranged to operate in at least an offloading mode in which the interconnect offload component is arranged to:
receive functional data from at least one interconnect client component of a signal processing device for communication to at least one destination component; and forward at least a part of the received functional data to at least one debug network of the signal processing device for communication to the at least one destination component via the at least one debug network.

2 . The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive functional data from the at least one interconnect client component for communication to at least one destination component; determine whether the received functional data comprises non-coherent data; and forward at least a part of the received functional data to the at least one debug network for communication to the at least one destination component if the at least part of the received functional data comprises non-coherent data.

3 . The interconnect offload component of claim 2 , wherein the interconnect offload component is arranged to forward at least a part of the received functional data to the at least one interconnect component of the signal processing device for communication to the at least one destination component if the at least part of the received functional data comprises coherent data.

4 . The interconnect offload component of claim 2 , wherein the interconnect offload component is arranged to determine whether the received functional data comprises non-coherent data based at least partly on a destination address for the received functional data.

5 . The interconnect offload component of claim 4 , wherein the interconnect offload component is arranged to compare the destination address of the received functional data to at least one offload address and to determine whether the received functional data comprises non-coherent data based at least partly on said comparison.

6 . (canceled)

7 . (canceled)

8 . (canceled)

9 . The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive functional data from the at least one interconnect client component for communication to at least one destination component; determine whether to forward at least a part of the received functional data to the at least one debug network for communication to the at least one destination component based at least partly on a set of rules; and forward at least a part of the received functional data to the at least one debug network for communication to the at least one destination component if so determined.

10 . (canceled)

11 . (canceled)

12 . The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive at least one direct memory access transaction from at least one direct memory access component of the signal processing device for communication to at least one memory component; and forward at least a part of the received direct memory access transaction to the at least one debug network of the signal processing device for communication to the at least one memory component via the at least one debug network.

13 . The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive at least one data packet comprising functional data from the at least one interconnect client component for communication to at least one destination component; forward a received payload component of the at least one data packet to the at least one debug network for communication to the at least one destination component; and forward a header component of the received at least one data packet to the at least one interconnect component for communication to the at least one destination component.

14 . (canceled)

15 . The interconnect offload component of claim 1 , wherein the interconnect offload component is configurable to enable and disable the offloading mode; the interconnect offload component being arranged to forward the received functional data to the at least one interconnect component of the signal processing device upon the offloading mode being disabled.

16 . (canceled)

17 . (canceled)

18 . An integrated circuit device comprising at least one die within a single integrated circuit package, comprising an interconnect offload component arranged to operate in at least an offloading mode in which the interconnect offload component is arranged to:
receive functional data from at least one interconnect client component of a signal processing device for communication to at least one destination component; and forward at least a part of the received functional data to at least one debug network of the signal processing device for communication to the at least one destination component via the at least one debug network.

19 . (canceled)

20 . (canceled)

21 . A memory access component for enabling access to at least one memory element for functional data transmitted over a debug network of a signal processing device; the memory access component being arranged to:
receive at least one debug format message transmitted over the debug network; extract functional data from the received at least one debug format message, said functional data originating from at least one interconnect client component of the signal processing device for communication to at least one memory element; and perform a direct memory access to the at least one memory element comprising the extracted functional data.

22 . The memory access component of claim 21 , wherein the memory access component is arranged to:
decode the received at least one debug form message into a payload and message attributes; determine whether the payload comprises functional data to be written to memory based at least partly on the decoded message attributes; and perform a direct memory access to the at least one memory element comprising at least a part of the decoded payload, upon determination that the payload comprises functional data to be written to memory.

23 . The memory access component of claim 22 , wherein the memory access component is arranged to determine whether the payload comprises functional data to be written to memory based at least partly on a type code within the decoded message attributes.

24 . The memory access component of claim 21 , wherein the memory access component is arranged to determine configuration attributes for performing the direct memory access based at least partly on the decoded message attributes.

25 . The memory access component of claim 24 , wherein the memory access component is arranged to lookup configuration attributes from a software configurable memory element based at least partly on the decoded message attributes.

26 . The memory access component of claim 25 , wherein the memory access component is arranged to lookup an address in memory from the software configurable memory element, and to perform the direct memory access to said address in memory.

27 . The memory access component of claim 26 , wherein the decoded message attr

Assignees

• Michalovich Benny
• Bar Ron
• Glickman Eran
• Shurin Dmitriy
• Freescale Semiconductor Inc

Inventors

• Michalovich Benny
• Bar Ron
• Glickman Eran
• Shurin Dmitriy

Classifications

• G06F11/3656 Primary

  using a specific debug interface · CPC title

• G06F11/3006 Primary

  where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50) · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F11/221

  to test buses, lines or interfaces, e.g. stuck-at or open line faults · CPC title