Supporting fault information delivery

Patent metadata

Field	Value
Publication number	US-2016378664-A1
Application number	US-201514752109-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.

First claim

What is claimed is:

1 . A processor comprising:
a memory controller unit to access an enclave page cache (EPC); and a processor core coupled to the memory controller unit, the processor core to:
detect a fault associated with accessing the EPC;
generate an error code associated with the fault, wherein the error code reflects an EPC-related fault cause; and
encode the error code into a data structure associated with the processor core, the data structure for monitoring a hardware state related to the processor core.

2 . The processor core of claim 1 , wherein the processor core is further to set an indicator in the data structure that indicates the fault is caused by access of a memory page of the EPC.

3 . The processor of claim 2 , wherein the processor core is further to set an indicator in the data structure that represents error code information associated with the EPC-related fault.

4 . The processor of claim 3 , wherein the error code information comprises several bit indicators indicating at least one of a memory page of the EPC that is accessed at an incorrect type, that the memory page access violated the EPC access permissions, and that the memory page of the EPC is write protected.

5 . The processor of claim 1 , wherein the processor core further to send an alert comprising information from the data structure associated with the EPC-related fault cause.

6 . The processor of claim 5 , wherein the alert further comprises information of a resolution for the EPC-related fault cause.

7 . The processor of claim 1 , wherein the processor core is further to:
check a data source associated with a kernel executed by the processing cores; and determine the source of the EPC-related fault based on at least the data source associated with the kernel and the data structure associated with the EPC-related fault cause.

8 . A method, comprising:
detecting, using a processing device, a fault associated with accessing an enclave page cache (EPC) in a memory device; generating an error code associated with the fault, wherein the error code reflects an EPC-related fault cause; and encoding the error code into a data structure associated with the processing device, the data structure for monitoring a hardware state related to the processing device.

9 . The method of claim 8 , further comprising setting an indicator in the data structure that indicates the fault is caused by access of a memory page of the EPC.

10 . The method of claim 9 , further comprising setting an indicator in the data structure that represents error code information associated with the EPC-related fault.

11 . The method of claim 10 , wherein the error code information comprises several bit indicators indicating at least one of a memory page of the EPC that is accessed at an incorrect type, that the memory page access violated the EPC access permissions, and that the memory page of the EPC is write protected.

12 . The method of claim 8 , further comprising sending an alert comprising information from the data structure associated with the EPC-related fault cause.

13 . The method of claim 12 , wherein the alert further comprises information of a resolution for the EPC-related page cause.

14 . The method of claim 8 , further comprising:
checking a data source associated with a kernel executed by the processing device; and determining the source of the EPC-related fault based on at least the data source associated with the kernel and the data structure associated with the EPC-related fault cause.

15 . A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system, cause the processing system to:
detect, using the processing system, a fault associated with accessing an EPC in memory; generate an error code associated with the fault, wherein the error code reflects an EPC-related fault cause; and encode the error code into a data structure associated with the processing system, the data structure for monitoring a hardware state related to the processing system.

16 . The computer-readable non-transitory storage medium of claim 15 , wherein executable instructions further causes the processing system to set an indicator in the data structure that indicates the fault is caused by access of a memory page of the EPC.

17 . The computer-readable non-transitory storage medium of claim 16 , wherein executable instructions further causes the processing system to set an indicator in the data structure that represents error code information associated with the EPC-related fault.

18 . The computer-readable non-transitory storage medium of claim 17 , wherein the error code information comprises several bit indicators indicating at least one of a memory page of the EPC that is accessed at an incorrect type, that the memory page access violated the EPC access permissions, and that the memory page of the EPC is write protected.

19 . The computer-readable non-transitory storage medium of claim 15 , wherein executable instructions further cause the processing system to send an alert comprising information from the data structure associated with the EPC-related fault cause.

20 . The computer-readable non-transitory storage medium of claim 19 , wherein the alert further comprises information of a resolution for the EPC-related fault cause.

Assignees

• Intel Corp

Inventors

• Leslie-Hurd Rebekah M
• Rozas Carlos V
• Mckeen Francis X
• Alexandrovich Ilya
• Shanbhogue Vedvyas
• Xing Bin
• Shanahan Mark W
• Johnson Simon P

Classifications

• G06F2212/402

  Encrypted data · CPC title

• G06F2212/312

  In storage controller · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/281

  Single cache · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title