Efficient instruction fusion by fusing instructions that fall within a counter-tracked amount of cycles apart

Patent metadata

Field	Value
Publication number	US-2016378487-A1
Application number	US-201615143518-A
Country	US
Kind code	A1
Filing date	Apr 30, 2016
Priority date	Oct 30, 2008
Publication date	Dec 29, 2016
Grant date	—

Abstract

A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

First claim

What is claimed is:

1 . A system comprising:
a plurality of cores to process instructions; a memory controller to connect the system to a system memory; one of the cores comprising:
an instruction memory to store instructions;
a decoder to decode instructions;
an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the core as a single instruction; and
the instruction fusion circuit to fuse the first and second instructions when both the first and second instructions have been stored in the instruction memory prior to issuance.

2 . The system as in claim 1 further comprising:
a cache shared by two or more of the plurality of cores.

3 . The system as in claim 1 further comprising:
a system interconnect to communicatively couple the system to one or more other components.

4 . A method comprising:
processing instructions on a plurality of cores; connecting a system to a system memory; storing the instructions in a an instruction memory; decoding the instructions; fusing a first instruction and a second instruction to form a fused instruction to be processed by the core as a single instruction; and fusing the first and second instructions when both the first and second instructions have been stored in the instruction memory prior to issuance.

5 . A system comprising:
means for processing instructions on a plurality of cores; means for connecting a system to a system memory; means for storing the instructions in an instruction memory; means for decoding the instructions; means for fusing a first instruction and a second instruction to form a fused instruction to be processed by the core as a single instruction; and means for fusing the first and second instructions when both the first and second instructions have been stored in the instruction memory prior to issuance.

6 . The system as in claim 5 further comprising:
means for communicatively coupling the system to one or more other components.

Assignees

• Ouziel Ido
• Rappoport Lihu
• Valentine Robert
• Gabor Ron
• Raghuvanshi Pankaj

Inventors

• Ouziel Ido
• Rappoport Lihu
• Valentine Robert
• Gabor Ron
• Raghuvanshi Pankaj

Classifications

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F9/30196 Primary

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F13/4063

  Device-to-bus coupling · CPC title