Instruction and logic for encoded word instruction compression

Patent metadata

Field	Value
Publication number	US-2016378481-A1
Application number	US-201514750638-A
Country	US
Kind code	A1
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A processor includes a memory and a decompressor. The memory is to store compressed instruction. The decompressor includes logic to receive a request for an instruction in the compressed instructions to be executed by the processor, determine a block in the memory including the requested instruction, and determine a start address of the block in the compressed instructions. The decompressor also includes logic decompress chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions.

First claim

What is claimed is:

1 . A processor, comprising:
a memory to store compressed instructions; and a decompressor, including:
a first logic to receive a request for an instruction in the compressed instructions to be executed by the processor;
a second logic to determine a block in the memory including the requested instruction;
a third logic to determine a start address of the block in the compressed instructions;
a fourth logic to decompress chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions.

2 . The processor of claim 1 , wherein the decompressor further includes a fifth logic to decompress chunks of the block to return columns of the parts of instruction information, the columns to include the parts of the VLIW instructions in uncompressed instruction memory.

3 . The processor of claim 1 , wherein the decompressor further includes a fifth logic to combine the parts to include uncompressed versions of the VLIW instructions.

4 . The processor of claim 1 , wherein the decompressor further includes a fifth logic to decompress a given chunk according to a prefix at the beginning of the chunk to define a compression scheme used to compress data words in the chunk.

5 . The processor of claim 1 , wherein the decompressor further includes a fifth logic to decompress data words in the given chunk to yield the parts of the VLIW instructions.

6 . The processor of claim 1 , wherein the decompressor further includes a fifth logic to decompress all chunks of the block upon receipt of the request for the instruction.

7 . The processor of claim 1 , wherein the decompressor further includes a fifth logic to decompress the chunks of the block according to time stationary encoding.

8 . A method, comprising:
storing compressed instructions in a memory to store compressed instructions; receiving a request for an instruction in the compressed instructions to be executed by the processor; determining a block in the memory including the requested instruction; determining a start address of the block in the compressed instructions; decompressing chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions, to yield the requested instruction.

9 . The method of claim 8 , further comprising decompressing chunks of the block to return columns of the parts of instruction information, the columns to include the parts of the VLIW instructions in uncompressed instruction memory.

10 . The method of claim 8 , further comprising combining the parts to include uncompressed versions of the VLIW instructions.

11 . The method of claim 8 , further comprising decompressing a given chunk according to a prefix at the beginning of the chunk to define a compression scheme used to compress data words in the chunk.

12 . The method of claim 8 , further comprising decompressing data words in the given chunk to yield the parts of the VLIW instructions.

13 . The method of claim 8 , further comprising decompressing all chunks of the block upon receipt of the request for the instruction.

14 . A system, comprising:
a memory to store compressed instructions; and a decompressor, including:
a first logic to receive a request for an instruction in the compressed instructions to be executed by a processor of the system;
a second logic to determine a block in the memory including the requested instruction;
a third logic to determine a start address of the block in the compressed instructions;
a fourth logic to decompress chunks of the block, a given chunk to include parts of a plurality of very-long instruction word (VLIW) instructions.

15 . The system of claim 14 , wherein the decompressor further includes a fifth logic to decompress chunks of the block to return columns of the parts of instruction information, the columns to include the parts of the VLIW instructions in uncompressed instruction memory.

16 . The system of claim 14 , wherein the decompressor further includes a fifth logic to combine the parts to include uncompressed versions of the VLIW instructions.

17 . The system of claim 14 , wherein the decompressor further includes a fifth logic to decompress a given chunk according to a prefix at the beginning of the chunk to define a compression scheme used to compress data words in the chunk.

18 . The system of claim 14 , wherein the decompressor further includes a fifth logic to decompress data words in the given chunk to yield the parts of the VLIW instructions.

19 . The system of claim 14 , wherein the decompressor further includes a fifth logic to decompress all chunks of the block upon receipt of the request for the instruction.

20 . The system of claim 14 , wherein the decompressor further includes a fifth logic to decompress the chunks of the block according to time stationary encoding.

Assignees

• Intel Corp

Inventors

• Leijten Jeroen

Classifications

• G06F9/30178 Primary

  of compressed or encrypted instructions · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/3853

  of compound instructions · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title