Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy

US9201652B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9201652-B2
Application numberUS-201113099463-A
CountryUS
Kind codeB2
Filing dateMay 3, 2011
Priority dateMay 3, 2011
Publication dateDec 1, 2015
Grant dateDec 1, 2015

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Abstract

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A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for decompressing instructions, the method comprising: fetching compressed instructions from a memory, wherein each compressed instruction comprises an X-index and a Y-index; fetching for each compressed instruction two lines of X-bit patterns from an X memory using the X-index masked for two line access and two lines of Y-bit patterns from a Y memory using the Y-index masked for two line access, wherein the two lines of patterns are fetched to ac…

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What does patent US9201652B2 cover?
A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed…
Who is the assignee on this patent?
Larin Sergei, Codrescu Lucian, Das Gupta Anshuman, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F9/30178. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).