Photomask, method of correcting error thereof, integrated circuit device manufactured by using the photomask, and method of manufacturing the integrated circuit device

US2016377973A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016377973-A1
Application numberUS-201615258163-A
CountryUS
Kind codeA1
Filing dateSep 7, 2016
Priority dateDec 9, 2013
Publication dateDec 29, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided are photomask and a method of correcting errors thereof. The photomask includes a multilayer reflection film covering one side surface of a substrate and an energy receiving layer covering the other side surface of the substrate. The method includes determining a local correction position on a frontside surface of the photomask according to a detected error of the photomask, and locally applying an energy beam to a backside surface region of the photomask aligned with the local correction position in a thickness direction of the photomask. The invention may be applicable to structures other than photomasks that benefit from modification of surface heights or selectively applied stress.

First claim

Opening claim text (preview).

1 . A photolithographic mask comprising: a substrate having a first surface and a second surface on an opposite side of the substrate from the first surface; a reflection film on the first surface of the substrate; a light absorber layer on the reflection film; and a stress inducing layer on the second surface of the substrate, the stress inducing layer configured to have selected locations alter a stress applied to the substrate to alter a shape of the photolithographic mask. 2 . The photolithographic mask of claim 1 , wherein the stress inducing layer comprises an amorphous material. 3 . The photolithographic mask of claim 2 , wherein the stress inducing layer comprises crystalline material. 4 . The photolithographic mask of claim 1 , wherein the stress inducing layer comprises a plurality of layers of a first material and a plurality of layers of a second material each interposed between corresponding ones of the plurality of layers of the first material. 5 . The photolithographic mask of claim 4 , wherein the first material comprises at least one of Al, Si and K. 6 . The photolithographic mask of claim 5 , wherein the second material comprises at least one of Nb, Mo, Ru and Pb. 7 . The photolithographic mask of claim 4 , wherein the first material comprises an amorphous portion and a crystalline portion. 8 . The photolithographic mask of claim 4 , wherein each layer of the plurality of layers of the first material comprise an amorphous portion and a crystalline portion. 9 . The photolithographic mask of claim 8 , wherein the crystalline portions of the plurality of layers of the first material provide stress to the substrate. 10 . The photolithographic mask of claim 9 , wherein each layer of the plurality of layers of the second material comprise an amorphous portion and a crystalline portion. 11 . The photolithographic mask of claim 1 , wherein the stress inducing layer comprises one or more depressions on a first surface, the one or more depressions corresponding to locations that induce stress on the substrate. 12 . The photolithographic mask of claim 1 , wherein the stress inducing layer comprises a first surface adjacent the second surface of the substrate and a second surface on an opposite side of the stress inducing layer from the first surface, wherein the one or more depressions are located on the second surface. 13 . The photolithographic mask of claim 12 , wherein the stress inducing layer comprises a first material having a crystalline state between each of the one or more depressions and the substrate and having an amorphous state at other locations. 14 . The photolithographic mask of claim 12 , wherein the stress inducing layer comprises a plurality of layers of a first material and a plurality of layers of a second material each interposed between corresponding ones of the plurality of layers of the first material. 15 . The photolithographic mask of claim 14 , wherein the first material and the second material have a crystalline state at locations between the one or more depressions and an amorphous state at other locations. 16 . The photolithographic mask of claim 1 , wherein the light absorbing layer is patterned to include openings to allow light to impinge on and reflect off of the reflection film. 17 . The photolithographic mask of claim 1 , wherein the stress inducing layer comprises a first material having a crystalline state and having an amorphous state at other locations 18 . The photolithographic mask of claim 17 , wherein the crystalline state of the first material exerts stress to the substrate. 19 - 49 . (canceled)

Assignees

Inventors

Classifications

  • H10P76/00Primary

    Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

  • G03F1/24Primary

    Reflection masks; Preparation thereof · CPC title

  • Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof · CPC title

  • Repair or correction of mask defects · CPC title

  • by charged particle beam [CPB], e.g. focused ion beam · CPC title

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What does patent US2016377973A1 cover?
Provided are photomask and a method of correcting errors thereof. The photomask includes a multilayer reflection film covering one side surface of a substrate and an energy receiving layer covering the other side surface of the substrate. The method includes determining a local correction position on a frontside surface of the photomask according to a detected error of the photomask, and locall…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P76/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).