Integrated circuit chip reliability qualification using a sample-specific expected fail rate

Patent metadata

Field	Value
Publication number	US-2016377674-A1
Application number	US-201514748704-A
Country	US
Kind code	A1
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

First claim

What is claimed is:

1 . A method comprising:
sorting integrated circuit chips manufactured according to a design into groups of integrated circuit chips, said groups corresponding to different process windows within a process distribution for said design; and, performing reliability qualification of said integrated circuit chips, said performing of said reliability qualification comprising:
setting pass/fail criteria for said integrated circuit chips;
given said pass/fail criteria, determining group fail rates for said groups;
selecting a sample of said integrated circuit chips from at least one of said groups;
identifying all specific groups from which said sample was selected;
determining percentages of said sample selected from said specific groups and specific group fail rates for said specific groups;
determining an expected sample fail rate for said sample, said expected sample fail rate being determined considering said percentages and said specific group fail rates;
stress testing said sample to determine an actual sample fail rate for said sample, given said pass/fail criteria; and,
comparing said expected sample fail rate to said actual sample fail rate.

2 . The method of claim 1 , further comprising: for each integrated circuit chip in each group, determining failure mechanism fail rates for different failure mechanisms on said integrated circuit chip as a function of a process window associated with said group and determining a chip fail rate based on said failure mechanism fail rates, each group fail rate being determined based on chip fail rates for any of said integrated circuit chips in said group.

3 . The method of claim 1 , said sample being selected from less than all of said groups.

4 . The method of claim 1 , said sample being non-random.

5 . The method of claim 1 , said group fail rates varying between said groups.

6 . The method of claim 1 , said expected sample fail rate being different from an expected overall fail rate.

7 . The method of claim 1 , further comprising developing any of design changes and process changes when said actual sample fail rate is greater than said expected sample fail rate.

8 . The method of claim 1 , further comprising allowing for incorporation of said integrated circuit chips into products when said actual sample fail rate is less than or equal to said expected sample fail rate.

9 . A method comprising:
sorting integrated circuit chips manufactured according to a design into groups of integrated circuit chips, said groups corresponding to different process windows within a process distribution for said design; and, performing reliability qualification of said integrated circuit chips, said performing of said reliability qualification comprising:
setting pass/fail criteria for said integrated circuit chips;
given said pass/fail criteria, determining group fail rates for said groups;
determining an expected overall fail rate for said integrated circuit chips, said expected overall fail rate being based on said group fail rates;
selecting a sample of said integrated circuit chips from at least one of said groups;
identifying all specific groups from which said sample was selected;
determining percentages of said sample selected from said specific groups and specific group fail rates for said specific groups;
determining an expected sample fail rate for said sample, said expected sample fail rate being determined considering said percentages and said specific group fail rates and being different from said expected overall fail rate;
stress testing said sample to determine an actual sample fail rate for said sample, given said pass/fail criteria; and,
comparing said expected sample fail rate to said actual sample fail rate.

10 . The method of claim 9 , further comprising: for each integrated circuit chip in each group, determining failure mechanism fail rates for different failure mechanisms on said integrated circuit chip as a function of a process window associated with said group and determining a chip fail rate based on said failure mechanism fail rates, each group fail rate being determined based on chip fail rates for any of said integrated circuit chips in said group.

11 . The method of claim 9 , said sample being selected from less than all of said groups.

12 . The method of claim 9 , said sample being non-random.

13 . The method of claim 9 , said group fail rates varying between said groups.

14 . The method of claim 9 , further comprising developing any of design changes and process changes when said actual sample fail rate is greater than said expected sample fail rate.

15 . The method of claim 9 , further comprising allowing for incorporation of said integrated circuit chips into products when said actual sample fail rate is less than or equal to said expected sample fail rate.

16 . A method comprising:
sorting integrated circuit chips manufactured according to a design into groups of integrated circuit chips, said groups corresponding to different process windows within a process distribution for said design; and, performing reliability qualification of said integrated circuit chips, said performing of said reliability qualification comprising:
setting pass/fail criteria for said integrated circuit chips;
given said pass/fail criteria, determining group fail rates for said groups;
determining an expected overall fail rate for said integrated circuit chips, said expected overall fail rate being based on said group fail rates;
selecting a sample of said integrated circuit chips from at least one of said groups;
identifying all specific groups from which said sample was selected;
determining percentages of said sample selected from said specific groups and specific group fail rates for said specific groups;
determining an expected sample fail rate for said sample, said expected sample fail rate being calculated as a sum of fail rate contributions from said specific groups, each fail rate contribution of each specific group comprising a product of a specific group fail rate determined for said specific group multiplied by a percentage of said sample selected from said specific group;
stress testing said sample to determine an actual sample fail rate for said sample, given said pass/fail criteria; and,
comparing said expected sample fail rate to said actual sample fail rate.

17 . The method of claim 16 , further comprising: for each integrated circuit chip in each group, determining failure mechanism fail rates for different failure mechanisms on said integrated circuit chip as a function of a process window associated with said group and determining a chip fail rate based on said failure mechanism fail rates, each group fail rate being determined based on chip fail rates for any of said integrated circuit chips in said group.

18 . The method of claim 16 , said sample being selected from less than all of said groups.

19 . The method of claim 16 , said group fail rates varying between said groups.

20 . The method of claim 16 , further comprising:
developing any of design changes and process changes when said actual sample fail rate is greater than said expected sample fail rate; and, allowing for incorporation of said integrated circuit chips into products when said actual sample fail rate is less than or equal to said expected sample fail rate.

Assignees

• IBM

Inventors

• Bickford Jeanne P
• Habib Nazmul
• Li Baozhen
• Wilder Tad J

Classifications

• G01R31/2894 Primary

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title

• G01R31/2642

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G05B19/418

  Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] · CPC title

• G05B19/4188

  characterised by CIM planning or realisation · CPC title