Microelectronic build-up layers and methods of forming the same

US2016374210A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016374210-A1
Application numberUS-201514905022-A
CountryUS
Kind codeA1
Filing dateFeb 16, 2015
Priority dateFeb 16, 2015
Publication dateDec 22, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.

First claim

Opening claim text (preview).

1 .- 25 . (canceled) 26 . A method of fabricating a microelectronic build-up layer, comprising: forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, wherein the microelectronic dielectric layer includes a first surface; forming a primer layer on the microelectronic dielectric layer first surface; forming a recess through the primer layer and into the microelectronic dielectric layer; and forming a metal layer adjacent the microelectronic dielectric layer within the recess. 27 . The method of claim 26 , wherein forming the recess through the primer layer and into the microelectronic dielectric layer comprises laser ablating a recess through the primer layer and into the microelectronic dielectric layer. 28 . The method of claim 26 , wherein forming the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprises an epoxy-polymer blend dielectric material. 29 . The method of claim 26 , wherein forming the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprises a metallization catalyst selected from the group consisting of palladium salts, silver salts, copper salts, platinum salts, and nickel salts. 30 . The method of claim 26 , wherein forming the primer layer on the microelectronic dielectric layer first surface comprises forming an organic polymer primer layer on the microelectronic dielectric layer first surface. 31 . The method of claim 30 , wherein forming the organic polymer primer layer on the microelectronic dielectric layer first surface comprises forming an organic polymer primer layer selected from the group consisting of epoxy-phenol materials and epoxy-imide materials. 32 . The method of claim 26 , wherein forming the metal layer on the dielectric material layer within the recess comprises: activating the microelectronic dielectric layer within the recess to form an activated layer within the dielectric material layer; and depositing a metal layer on the activated layer. 33 . The method of claim 32 , wherein activating the microelectronic dielectric layer comprises immersing the microelectronic dielectric layer and primer layer in an activation solution. 34 . The method of claim 33 , wherein immersing the microelectronic dielectric layer and primer layer in an activation solution comprising immersing the microelectronic dielectric layer and primer layer in a dimethylborane activation solution. 35 . The method of claim 32 , wherein depositing a metal layer on the activated layer comprises immersing the activated layer in a deposition solution. 36 . The method of claim 35 , wherein immersing the activated layer in a deposition solution comprising immersing activated layer in an aqueous deposition solution comprising a metal salt and a reducing agent. 37 . The method of claim 36 , wherein immersing the activated layer in an aqueous deposition solution comprising a metal salt and a reducing agent comprises immersing the activated layer in an aqueous deposition solution comprising a copper salt and a reducing agent. 38 . A microelectronic build-up layer, comprising: a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, wherein the microelectronic dielectric layer includes a first surface; a primer layer on the microelectronic dielectric layer first surface; a recess through the primer layer and into the microelectronic dielectric layer; and a metal layer adjacent the microelectronic dielectric layer within the recess. 39 . The microelectronic build-up layer of claim 38 , wherein the recess through the primer layer and into the microelectronic dielectric layer comprises a laser ablated recess through the primer layer and into the microelectronic dielectric layer. 40 . The microelectronic build-up layer of claim 38 , wherein the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprises an epoxy-polymer blend dielectric material. 41 . The microelectronic build-up layer of claim 38 , wherein the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprises a metallization catalyst selected from the group consisting of palladium salts, silver salts, copper salts, platinum salts, and nickel salts. 42 . The microelectronic build-up layer of claim 38 , wherein the primer layer on the microelectronic dielectric layer first surface comprises an organic polymer primer layer on the microelectronic dielectric layer first surface. 43 . The microelectronic build-up layer of claim 42 , wherein the organic polymer primer layer on the microelectronic dielectric layer first surface comprises an organic polymer primer layer selected from the group consisting of epoxy-phenol materials and epoxy-imide materials. 44 . The microelectronic build-up layer of claim 38 , further comprising an activated layer disposed between the metal layer and the dielectric material layer within the recess. 45 . The microelectronic build-up layer of claim 38 , wherein the metal layer comprises a conformal metal layer. 46 . The microelectronic build-up layer of claim 38 , wherein the metal layer comprises a copper layer. 47 . A electronic system, comprising: a board; and a microelectronic component attached to the board, wherein the microelectronic component includes microelectronic build-up layer, comprising: a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, wherein the microelectronic dielectric layer includes a first surface; a primer layer on the microelectronic dielectric layer first surface; a recess through the primer layer and into the microelectronic dielectric layer; and a metal layer adjacent the microelectronic dielectric layer within the recess. 48 . The electronic system of claim 47 , wherein the recess through the primer layer and into the microelectronic dielectric layer comprises a laser ablated recess through the primer layer and into the microelectronic dielectric layer. 49 . The electronic system of claim 47 , wherein the primer layer on the microelectronic dielectric layer first surface comprises an organic polymer primer layer on the microelectronic dielectric layer first surface. 50 . The electronic system of claim 47 , further comprising an activated layer disposed between the metal layer and the dielectric material layer within the recess.

Assignees

Inventors

Classifications

  • using a liquid · CPC title

  • Insulating materials thereof · CPC title

  • H10W70/05Primary

    of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

  • the principal metal being copper · CPC title

  • by forming openings in the dielectric parts · CPC title

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What does patent US2016374210A1 cover?
A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric la…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/05. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).