Transmitter, a receiver, a data transfer system and a method of data transfer

Patent metadata

Field	Value
Publication number	US-2016374029-A1
Application number	US-201615166315-A
Country	US
Kind code	A1
Filing date	May 27, 2016
Priority date	Jun 16, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

A data transfer system, a method of data transfer and a corresponding transmitter and receiver are disclosed. A communication protocol between the transmitter and receiver is defined using a set of valid transmission states for communication from the transmitter to the receiver and a set of valid acknowledgement states for transmission from the receiver to the transmitter. A Hamming distance between patterns of zeroes, and between patterns of ones, in valid states of each of these sets is at least one and the transmitter is arranged to transition between a number of transmission states in response to the reception of an acknowledgement state from the receiver which matches a transmission state it has sent to the receiver on a request bus. A communication protocol which is robust across a multi-voltage and/or clock domain interface is thus provided.

First claim

I claim:

1 . A data transfer system comprising:
a data bus, a request bus and an acknowledge bus; a transmitter to assert a current transmission state on the request bus in accordance with a communication protocol, wherein the current transmission state is indicative of a state of the transmitter with respect to data transfer via the data bus; and a receiver to read a received transmission state from the request bus in accordance with the communication protocol and to assert an acknowledgement state on the acknowledge bus when the received transmission state is a valid transmission state of a set of valid transmission states according to the communication protocol, wherein the transmitter is arranged to read a received acknowledgement state from the acknowledge bus in accordance with the communication protocol, and the transmitter is responsive to reception of a valid acknowledgement state of a set of valid acknowledgement states according to the communication protocol, when the valid acknowledgement state corresponds to the state of the transmitter, to transition the state of the transmitter with respect to data transfer via the data bus, wherein a Hamming distance between patterns of zeroes, and a Hamming distance between patterns of ones, in valid transmission states of the set of valid transmission states is at least one, and wherein a Hamming distance between patterns of zeroes, and a Hamming distance between patterns of ones, in valid acknowledgement states of the set of valid acknowledgement states is at least one.

2 . The data transfer system as claimed in claim 1 , wherein the set of valid transmission states and the set of valid acknowledgement states each have constant parity value.

3 . The data transfer system as claimed in claim 1 , wherein the set of valid transmission states and the set of valid acknowledgement states each comprise a test mode state which has the constant parity value.

4 . The data transfer system as claimed in claim 3 , wherein the data bus comprises a transmitter-to-receiver data bus and a receiver-to-transmitter data bus, and the receiver is responsive to the received transmission state being the test mode state to transmit on the receiver-to-transmitter data bus data received on the transmitter-to-receiver data bus.

5 . The data transfer system as claimed in claim 1 , wherein a bit pattern of the acknowledgement state asserted on the acknowledge bus by the receiver is identical to the received transmission state read by the receiver from the request bus.

6 . The data transfer system as claimed in claim 1 , wherein a bit pattern of the acknowledgement state asserted on the acknowledge bus by the receiver is non-identical to the received transmission state read by the receiver from the request bus.

7 . The data transfer system as claimed in claim 1 , wherein the set of valid transmission states and the set of valid acknowledgement states each comprise a standby state in which the transmitter does not seek to perform data transfer via the data bus.

8 . The data transfer system as claimed in claim 1 , wherein the transmitter comprises clamping circuitry to hold the current transmission state asserted on the request bus in a powered-down state which is not comprised in the set of valid transmission states according to the communication protocol, and the transmitter is arranged to enter a transmitter low-power state when the powered-down state is asserted on the request bus, and the receiver is responsive to reading the powered-down state from the request bus to enter a receiver low-power state.

9 . The data transfer system as claimed in claim 8 , wherein the request bus is clamped active-low for the powered-down state.

10 . The data transfer system as claimed in claim 8 , wherein the receiver comprises wake-up circuitry responsive to a change in value of any bit on the request bus to cause the receiver to exit the receiver low-power state.

11 . The data transfer system as claimed in claim 7 , wherein the transmitter comprises clamping circuitry to hold the current transmission state asserted on the request bus in the standby state, and the transmitter is arranged to enter a transmitter low-power state when the clamping circuitry holds the current transmission state asserted on the request bus in the standby state, and the receiver is responsive to reading the standby state from the request bus to enter a receiver low-power state.

12 . The data transfer system as claimed in claim 11 , wherein the standby state is a multi-bit signal in which a single bit is asserted, and the receiver comprises wake-up circuitry responsive to the single bit not being asserted to cause the receiver to exit the low-power state.

13 . The data transfer system as claimed in claim 8 , wherein when the transmitter exits the transmitter low-power state in preparation for data transfer via the data bus and asserts the current transmission state on the request bus, the transmitter is arranged to enter a transmitter low-power mode until a change in the received acknowledgement state occurs on the acknowledge bus.

14 . The data transfer system as claimed in claim 1 , wherein the set of valid transmission states comprises two active data transmission states used by the transmitter when actively asserting valid data on the data bus, and any active change in a data value asserted on the data bus by the transmitter is accompanied by a change between the two active data transmission states.

15 . The data transfer system as claimed in claim 14 , wherein the receiver is responsive to reading one of the two active data transmission states from the request bus to sample data from the data bus.

16 . The data transfer system as claimed in claim 1 , wherein the transmitter and the receiver are in different clock domains, and
the receiver comprises receiver synchronisation circuitry to sample the request bus in a clock domain of the receiver to provide signals for receiver decode circuitry to determine the received transmission state, and the transmitter comprises transmitter synchronisation circuitry to sample the acknowledgment bus in a clock domain of the transmitter to provide signals for transmitter decode circuitry to determine the received acknowledgement state.

17 . The data transfer system as claimed in claim 1 , wherein the receiver comprises multiple data reception buffers individually corresponding to multiple data sources of data to be transferred via the data bus,
the multiple data reception buffers are each arranged to provide a readiness signal for transmission to the transmitter, and the transmitter is responsive to at least one readiness signal indicating that the corresponding data reception buffer is ready to receive data to select a data source for data transfer via the data bus and to indicate the data source via the data bus.

18 . The data transfer system as claimed in claim 17 , comprising a readiness bus to carry the readiness signals for the multiple data reception buffers.

19 . The data transfer system as claimed in claim 17 , wherein the acknowledgment bus is arranged to carry the readiness signals for the multiple data reception buffers.

20 . A method of data transfer in a data transfer system comprising a data bus, a request bus and an acknowledge bus, the method comprising the steps of:
asserting a current transmission state of a transmitter on the request bus in accordance with a communication protocol, wherein the current transmission state is indicative of a sta

Assignees

• Advanced Risc Mach Ltd

Inventors

• Flynn David Walter

Classifications

• G06F13/4269 Primary

  using a handshaking protocol, e.g. Centronics connection · CPC title

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L1/0063

  Single parity check · CPC title

• G06F1/3253

  Power saving in bus · CPC title