Systems and methods for reordering packet transmissions in a scalable memory system protocol

Patent metadata

Field	Value
Publication number	US-9600191-B2
Application number	US-201514724489-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Jun 2, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. The processor may also perform the plurality of data operations in a first order based on the type of memory component indicated in the transaction window field of each of the plurality of packets.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of memory components configured to store data;
a processor communicatively coupled to the plurality of memory components, wherein the processor is configured to:
receive a plurality of packets associated with a plurality of data operations, wherein each of the plurality of packets comprises a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet; and
perform the plurality of data operations in an order based on the type of memory component indicated in the transaction window field of each of the plurality of packets.

2. The memory device of claim 1 , wherein the processor is configured to perform a first portion of the plurality of data operations before a second portion of the plurality of operations, wherein the first portion is associated with a first memory type of the memory types and the second portion is associated with a second memory type of the memory types.

3. The memory device of claim 2 , wherein the first memory type is associated with a first set of requests having a first latency and the second memory type is associated with a second set of requests having a second latency that is larger than the first latency.

4. The memory device of claim 1 , wherein the processor is configured to perform the plurality of data operations in the order by:
determining whether a first data operation of the plurality of data operations can be performed, wherein the first data operation corresponds to a first packet of the plurality of packets and a first transaction window;
identifying a second data operation of the plurality of data operations, wherein the second data operation corresponds to a second packet of the plurality of packets and a second transaction window; and
performing the second data operation when the first data operation cannot be performed, wherein the first transaction window is different from the second transaction window.

5. The memory device of claim 4 , wherein the first data operation cannot be performed when a memory address associated with the first data operation is busy.

6. The memory device of claim 1 , wherein the memory types comprise a Dynamic Random-Access Memory (DRAM), Static Random-Access Memory (SRAM), a NAND memory, or any combination thereof.

7. The memory device of claim 1 , wherein the transaction window field comprises a minimum transaction size for each of the plurality of packets.

8. The memory device of claim 1 , wherein the processor is configured to send a reorder message to another processor that transmitted the plurality of packets, wherein the reorder message indicates the first order, wherein the order is different from an order in which the plurality of packets are transmitted.

9. A system, comprising:
a memory device comprising a processor;
a receiving component communicatively coupled to the processor, wherein the receiving component is configured to:
receive a plurality of packets from the processor, wherein the plurality of packets is transmitted in a first order;
determine whether a plurality of data operations that corresponds to the plurality of packets should be performed in the first order based on availability of a memory component associated with the plurality of data operations;
determine a second order to perform the data operations when the plurality of data operations should not be performed in the first order, wherein each of the plurality of packets is associated with a transaction window indicating a type of memory component associated with a respective data operation of the respective packet, and wherein the receiving component determines the second order by identifying a portion of the plurality of packets having a same transaction window; and
send a reorder message comprising the second order to the memory processor.

10. The system of claim 9 , wherein the receiving component determines that the plurality of data operations should not be performed in the first order when at least one of the plurality of data operations cannot be performed due to an unavailable memory address or a busy memory address.

11. The system of claim 9 , wherein the receiving component determines the second order based on whether at least one of the plurality of data operations is dependent on another one of the plurality of data operations being performed before the at least one of the plurality of data operations.

12. The system of claim 9 , wherein the receiving component is configured to send a plurality of response packets to the processor according to the second order after sending the reorder message.

13. The system of claim 9 , wherein the processor is configured to associate each of a plurality of response packets received from the receiving component after receiving the reorder message to a respective packet of the plurality of packets according to an order indicated in the reorder message.

14. The system of claim 9 , wherein the reorder message comprises a new order number for each packet of a portion of the plurality of the packets that the processor has not received a corresponding response packet from the receiving component.

15. The system of claim 14 , wherein the new order number is associated with a relative position in a queue of a plurality of response packets expected to be received by the processor.

16. A method comprising:
transmitting, via a processor, a plurality of packets to a receiving component configured to perform a plurality of data operations based on the plurality of packets;
receiving, via the processor, a reorder message regarding a plurality of response packets being transmitted from the receiving component, wherein the reorder message is associated with a portion of the plurality of packets transmitted to the receiving component, wherein the processor has not received a response packet associated with any packet of the portion of plurality of packets;
receiving, via the processor, the plurality of response packets from the receiving component; and
associating, via the processor, each of the plurality of response packets with a corresponding packet of the portion of the plurality of packets.

17. The method of claim 16 , wherein the reorder message comprises an order in which each of the plurality of response packets is associated with the corresponding packet of the portion of the plurality of packets based on a relative order of the portion of the plurality of packets in a queue.

18. The method of claim 16 , comprising:
renaming each packet of the portion of the plurality of packets based on a relative order of the portion of the plurality of packets in a queue;
generating a modified order of the relative order based on a preferred order to perform a portion of the plurality of data operations that correspond to the portion of the plurality of packets; and
generating the reorder message based on the modified order.

19. A system, comprising:
a processor configured to generate a plurality of packets associated with a plurality of data operations; and
a receiving component configured to:
receive the plurality of packets from the processor, wherein the plurality of packets is received in a first order that corresponds to an order in which the plurality of data operations are to be performed;
send a plurality of reorder messages when the plurality of data operations cannot be performed in the order;
append each received packet of a portion of the plurality of packets with a sequence number when the

Assignees

• Micron Technology Inc

Inventors

• Pawlowski J Thomas

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title