Implementation of a One Time Programmable Memory Using a MRAM Stack Design

Patent metadata

Field	Value
Publication number	US-2016293268-A1
Application number	US-201615078182-A
Country	US
Kind code	A1
Filing date	Mar 23, 2016
Priority date	Apr 3, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.

First claim

What is claimed is:

1 . A magnetic one-time-programmable memory cell comprising:
a magnetic tunnel junction (MTJ) device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is a write voltage for an MRAM cell; and a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device.

2 . The magnetic one-time-programmable memory cell of claim 1 wherein the area of the MTJ device is chosen to be approximately 20% smaller in diameter such that the resistance of the MTJ device is approximately 50% greater than an MTJ device of the MRAM cell.

3 . The magnetic one-time-programmable memory cell of claim 1 wherein program voltage is approximately 1.5V.

4 . The magnetic one-time-programmable memory cell of claim 1 wherein when the program voltage is applied across the magnetic one-time-programmable memory cell, the resistance of the MTJ device and the gating transistor form a voltage divider such that the voltage across the MTJ device is determined by the equation:

V
MTJ

=

V
BL

·

1

1
+

R
MOST

R
MTJ

Where:
V MTJ is the voltage developed across the MTJ device,
VBL is the voltage applied across the magnetic one-time-programmable memory cell,
R MOST is the resistance of the gating MOS transistor, and
R MTJ is the resistance of the MTJ device.

5 . The magnetic one-time-programmable memory cell of claim 1 wherein the breakdown of the tunnel barrier insulating layer causes the fixed magnetic layer and the free magnetic layer to short, thus programming the magnetic one-time-programmable memory cell to the low resistance state.

6 . The magnetic one-time-programmable memory cell of claim 1 wherein a structure and size of the gating MOS transistor is equivalent to the structure and size of a gating MOS transistor of an MRAM memory cell.

7 . The magnetic one-time-programmable memory cell of claim 1 wherein the drain of the gating MOS transistor is connected to the first electrode of the MTJ device, a source of the gating MOS transistor provides a first connection to external circuitry, and a gate of the gating MOS transistor provides a second connection to external circuitry.

8 . The magnetic one-time-programmable memory cell of claim 7 wherein the second electrode of the MTJ device provides a third connection to external circuitry.

9 . A magnetic one-time-programmable memory array comprises:
a plurality of magnetic one-time-programmable memory cells arranged in rows and columns, wherein each magnetic one-time-programmable memory cell comprises:
a magnetic tunnel junction (MTJ) device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, wherein a diameter of the MTJ device is chosen such that the tunnel barrier insulating is broken down by a program voltage applied across the magnetic one-time-programmable memory cell that is a write voltage for an MRAM cell; and
a gating metal oxide semiconductor (MOS) transistor serially connected to the MTJ device;
a plurality of pairs of bit lines wherein a first bit line of the pairs of bit lines is connected to the second electrode of the MTJ device of the magnetic one-time-programmable memory cells of an associated column of the array, a second bit line of the pairs of bit lines is connected to the source of the gating MOS transistor of the magnetic one-time-programmable memory cells of the associated column of the array; a plurality of word lines wherein each word line is associated with each row of the plurality of magnetic one-time-programmable memory cells such that the gates of gating MOS transistors of each row of the magnetic one-time-programmable memory cells is connected to the word line associated with each row of the magnetic one-time-programmable memory cells.

10 . The magnetic one-time-programmable memory array of claim 9 further comprising a column decoder connected to the pairs of bit lines linked with the columns of the magnetic one-time-programmable memory cells, wherein the column decoder applies the program voltage across to selected columns of the magnetic one-time-programmable memory cells for selectively programming the magnetic one-time-programmable memory cells on one selected row.

11 . The magnetic one-time-programmable memory array of claim 9 further comprising a row decoder connected to the word lines that are joined to each of the rows of the magnetic one-time-programmable memory cells, wherein the row decoder activates the gating MOS transistor for one selected row for reading and writing the selected magnetic one-time-programmable memory cells.

12 . The magnetic one-time-programmable memory array of claim 10 wherein the column decoder further comprises a sense amplifier that receives read currents when a read voltage is applied to the pairs of bit lines for determining the digital data as programmed into the magnetic one-time-programmable memory array.

13 . The magnetic one-time-programmable memory array of claim 12 further comprises at least two columns of reference magnetic one-time-programmable memory cells that are programmed and connected to the column decoder to provide a reference voltage for the sense amplifier.

14 . The magnetic one-time-programmable memory array of claim 13 wherein one column of the reference magnetic one-time-programmable memory cells is programmed to have the low resistance of a programmed magnetic one-time-programmable memory cell and a second column has the high resistance of the un-programmed magnetic one-time-programmable memory cell, wherein a current of the two columns is combined such that a reference voltage is provided for the sense amplifier.

15 . An integrated circuit constructed on a semiconductor substrate comprising:
at least one magnetic one-time-programmable memory array comprising:
a plurality of magnetic one-time-programmable memory cells arranged in rows and columns, wherein each magnetic one-time-programmable memory cell comprises:
a magnetic tunnel junction (MTJ) device comprising a fixed magnetic layer fabricated on a first electrode, a tunnel barrier insulating layer fabricated upon the fixed magnetic layer, a free magnetic layer fabricated on the tunnel barrier insulating layer, and a second electrode fabricated on the free magnetic layer, wherein a diameter of the MTJ device is chosen such that the tunnel barrier ins

Assignees

• Headway Tech Inc

Inventors

• Jan Guenole
• Wang Po-Kang
• Lee Yuan-Jen
• Zhu Jian
• Liu Huanlong

Classifications

• G11C11/005 Primary

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/409

  Read-write [R-W] circuits · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title