Array substrate, method for producing the same and display device

Patent metadata

Field	Value
Publication number	US-2016365458-A1
Application number	US-201515104524-A
Country	US
Kind code	A1
Filing date	Nov 10, 2015
Priority date	Dec 22, 2014
Publication date	Dec 15, 2016
Grant date	—

Abstract

Disclosed are an array substrate, a method for producing the same and a display device including the same. The array substrate includes a substrate; a first gate, a first gate insulation layer, an active layer, a second gate insulation layer, a second gate, a third gate insulation layer and source and drain electrodes provided on the substrate in sequence. Two side regions outside a region of the active layer corresponding to the second gate are source and drain-lightly doped regions and source and drain-heavily doped regions, respectively. The source and drain electrodes are contacted with the heavily doped source and drain regions, respectively. The first gate is provided below the lightly doped drain region corresponding to the drain electrode, or the first gate includes first and second sub parts which are respectively provided below the lightly doped source and drain regions corresponding to the source and drain electrodes respectively.

First claim

1 . An array substrate, comprising:
a substrate; a first gate and a first gate insulation layer provided on the substrate in sequence; an active layer provided on the first gate insulation layer; a second gate insulation layer, a second gate, a third gate insulation layer and source and drain electrodes, which are provided on the active layer in sequence, wherein the source and drain electrodes are provided on the third gate insulation layer; wherein two side regions outside a region of the active layer corresponding to the second gate are lightly doped source and drain regions and heavily doped source and drain regions respectively, wherein the lightly doped source region and the lightly doped drain region are immediately adjacent to the second gate, the heavily doped source region is immediately adjacent to the lightly doped source region, the heavily doped drain region is immediately adjacent to the lightly doped drain region, and the source and drain electrodes are electrically connected with the heavily doped source and drain regions, respectively; wherein the first gate is provided below the lightly doped drain region corresponding to the drain electrode, or the first gate includes a first sub part of the first gate and a second sub part of the first gate, which are respectively provided below the lightly doped source region and the lightly doped drain region corresponding to the source and drain electrodes respectively.

2 . The array substrate as claimed in claim 1 , wherein the active layer is an active layer in a polycrystalline state formed by crystallizing an amorphous oxide.

3 . The array substrate as claimed in claim 2 , wherein the active layer is made of low temperature poly-silicon.

4 . The array substrate as claimed in claim 1 , wherein the third gate insulation layer and the second gate insulation layer are provided with via holes, through which the source and drain electrodes are contacted and connected with the heavily doped source and drain regions, respectively.

5 . The array substrate as claimed in claim 1 , wherein a buffer layer is provided between the substrate and the first gate.

6 . A display device, comprising the array substrate as claimed in claim 1 .

7 . A method for producing an array substrate, comprising:
forming a pattern of a first gate on a substrate; forming a first gate insulation layer on the substrate subjected to the preceding step; forming an active layer on the substrate subjected to the preceding steps; forming a second gate insulation layer on the substrate subjected to the preceding steps; forming a pattern of a second gate on the substrate subjected to the preceding steps; source and drain-heavily doping and source and drain-lightly doping two side regions outside a region of the active layer corresponding to the second gate respectively, wherein the lightly doped source region and the lightly doped drain region are immediately adjacent to the active layer corresponding to the second gate, the heavily doped source region is immediately adjacent to the lightly doped source region, and the heavily doped drain region is immediately adjacent to the lightly doped drain region; forming a third gate insulation layer on the substrate subjected to the preceding steps, and forming via holes thereon; forming a pattern of source and drain electrodes on the substrate subjected to the preceding steps, wherein the source and drain electrodes are electrically connected with the heavily doped source and drain regions through the via holes, respectively; wherein the first gate is provided below the lightly doped drain region corresponding to the drain electrode, or the first gate includes a first sub part of the first gate and a second sub part of the first gate, which are respectively provided below the lightly doped source region and the lightly doped drain region corresponding to the source and drain electrodes respectively.

8 . The method as claimed in claim 7 , wherein the active layer is an active layer in a polycrystalline state formed by crystallizing an amorphous oxide.

9 . The method as claimed in claim 8 , wherein the active layer is made of low temperature poly-silicon, and the crystallizing process is an excimer laser annealing.

10 . The method as claimed in claim 7 , wherein the step of source and drain-heavily doping and source and drain-lightly doping two side regions outside a region of the active layer corresponding to the second gate comprises steps of:
retaining a photo resist after the etching for forming the second gate, wherein there is a deviation in critical dimension between the photo resist and the second gate, and heavily doping a region of the active layer which is not shielded by the photo resist; peeling off the photo resist and lightly doping a region of the active layer which is not shielded by the second gate.

11 . The method as claimed in claim 7 , further comprising:
forming a buffer layer on the substrate before forming the pattern of the first gate on the substrate.

12 . The method as claims in claim 10 , further comprising:
forming a buffer layer on the substrate before forming the pattern of the first gate on the substrate.

13 . The display device as claimed in claim 6 , wherein the active layer of the array substrate is an active layer in polycrystalline state formed by crystallizing an amorphous oxide.

14 . The display device as claimed in claim 13 , wherein the active layer is made of low temperature poly-silicon.

15 . The display device as claimed in claim 6 , wherein the third gate insulation layer and the second gate insulation layer of the array substrate are provided with via holes, through which the source and drain electrodes are contacted and connected with the heavily doped source and drain regions, respectively.

16 . The display device as claimed in claim 6 , wherein a buffer layer is provided between the substrate and the first gate.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shi Lei
• Xu Xiaowei

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P30/22

  using masks · CPC title

• H10P14/3808

  using laser beams · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title