System and method for chemical mechanical planarization process prediction and optimization

Patent metadata

Field	Value
Publication number	US-2016365253-A1
Application number	US-201514950899-A
Country	US
Kind code	A1
Filing date	Nov 24, 2015
Priority date	Jun 9, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

A system for processing a semiconductor wafer includes a database configured to store data including relationships between device pattern characteristics, chemical mechanical polishing (CMP) conditions, and CMP performance, a data analyzer configured to predict performance of a CMP process to be performed on a wafer based on wafer design data and the relationships included in the database, and an output device configured to output the predicted performance of the CMP process.

First claim

What is claimed is:

1 . A system for processing a semiconductor wafer, comprising:
a database configured to store data including relationships between device pattern characteristics, chemical mechanical polishing (CMP) conditions, and CMP performance; a data analyzer configured to predict performance of a CMP process to be performed on a wafer based on wafer design data and the relationships included in the database; and an output device configured to output the predicted performance of the CMP process.

2 . The system of claim 1 , wherein the device pattern characteristics include at least one of pattern densities or line widths.

3 . The system of claim 1 , wherein the CMP conditions include at least one of pad life, polish head down force, rotation speed, slurry flow, over-polish (O.P.) time, over-polish (O.P.) amount, within wafer (WIW) range, and zone pressure.

4 . The system of claim 1 , wherein the CMP performance includes at least one of dishing amount, erosion amount, and remaining thickness of a stop layer.

5 . The system of claim 1 , wherein the relationships vary across the wafer.

6 . The system of claim 1 , wherein the relationships include a relationship between a particular pattern characteristic and a particular type of CMP performance at a particular location on a wafer resulting from a CMP process having a particular CMP condition.

7 . The system of claim 1 , wherein the data analyzer is further configured to determine optimized conditions of the CMP process to be performed on the wafer based on the wafer design data and the relationships included in the database.

8 . The system of claim 7 , further comprising a CMP apparatus configured to perform the CMP process on the wafer by using the optimized conditions.

9 . The system of claim 1 , wherein, when the data analyzer is configured to predict performance of a CMP process to be performed on a wafer based on wafer design data and the relationships included in the database, the data analyzer is configured to:
obtain the wafer design data; calculate pattern characteristics of the wafer design data; obtain CMP conditions of the CMP process to be performed on the wafer; and predict the performance of the CMP process on the wafer based on the calculated pattern characteristics, the obtained CMP conditions, and the relationships included in the database.

10 . The system of claim 1 , wherein the data analyzer is further configured to:
determine whether it is necessary to add dummy patterns in at least one area in the wafer; and in response to determining that it is necessary to add dummy patterns, modify wafer design data to add dummy patterns in the at least one area.

11 . The system of claim 10 , wherein the output device is further configured to output the modified wafer design data.

12 . The system of claim 8 , wherein the data analyzer is further configured to:
predict CMP performance of the CMP process on the wafer based on the wafer design data, the optimized conditions, and the relationships included in the database; after performing the CMP process on the wafer by using the optimized conditions, collect CMP performance of the CMP process on the wafer, and determine whether the collected CMP performance matches the predicted CMP performance; and in response to determining that the collected CMP performance does not match the predicted CMP performance, modify the relationships included in the database.

13 . A method for processing a semiconductor wafer, comprising:
establishing a database including relationships between pattern characteristics, chemical mechanical polishing (CMP) conditions, and CMP performance; predicting performance of a CMP process to be performed on a wafer based on wafer design data and the relationships included in the database; and outputting the predicted performance of the CMP process.

14 . The method of claim 13 , wherein the establishing the database includes:
designing and fabricating a plurality of test wafers each including a plurality of test patterns in the form of step heights, the plurality of test patterns having various pattern characteristics; performing, on each of the plurality of test wafers, one of a plurality of CMP processes having various CMP conditions; collecting CMP performance of the CMP processes on the test wafers; and determining relationships between pattern characteristics, CMP conditions, and CMP performance based on the pattern characteristics of the test patterns formed on the test wafers, the CMP conditions of the CMP processes performed on the test wafers, and the CMP performance of the CMP processes performed on the test wafers; and storing the determined relationships in the CMP database.

15 . The method of claim 14 , wherein each of the plurality of test wafers includes a plurality of dies having substantially the same layout, and each of the plurality of dies includes the plurality of test patterns having various pattern characteristics.

16 . The method of claim 14 , further including:
performing, on a first test wafer, a first CMP process having a first CMP process condition; and performing, on a second test wafer, a second CMP process having a second CMP process condition different from the first CMP process condition.

17 . The method of claim 14 , wherein each one the plurality of test patterns has at least various pattern densities or various line widths.

18 . The method of claim 14 , wherein the collecting CMP performance of the CMP processes on the test wafers includes measuring surface characteristics of the test wafers resulting from performing the CMP processes.

19 . A semiconductor device, comprising:
a substrate; a plurality of protrusions formed on the substrate and spaced apart from each other; a plurality of first material layers formed on portions of side surfaces of the plurality of protrusions, exposing portions of each of the protrusions; a plurality of stop layers formed on side surfaces of the first material layers; and a plurality of second material layers respectively formed between adjacent ones of the protrusions; wherein a height of an exposed portion of a first protrusion on one portion of the substrate is the same as a height of an exposed portion of a second protrusion disposed on another portion of the substrate.

20 . The semiconductor device of claim 19 , wherein
the plurality of protrusions are formed of polysilicon, the plurality of stop layers are formed of silicon nitride, the plurality of first material layers are formed of silicon oxide, and the plurality of second material layers are formed of silicon oxide.

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Kuang-Wei
• Chen Chun-Fu
• Luoh Tuung

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title