Chip-scale package and semiconductor device assembly

Patent metadata

Field	Value
Publication number	US-2016359295-A1
Application number	US-201514731510-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A chip-scale package for an edge-emitting semiconductor device and a semiconductor device assembly including such a chip-scale package are provided. The chip-scale package includes an edge-emitting semiconductor device chip, a top submount disposed on a top surface of the chip, and a bottom submount disposed on a bottom surface of the chip. The top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area.

First claim

We claim:

1 . A chip-scale package comprising:
an edge-emitting semiconductor device chip, having a chip area, comprising a top surface and an opposite bottom surface; a top submount, having a top-submount area, disposed on the top surface of the chip; and a bottom submount, having a bottom-submount area, disposed on the bottom surface of the chip; wherein the top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area.

2 . The chip-scale package of claim 1 , wherein the chip includes a single edge-emitting semiconductor device.

3 . The chip-scale package of claim 2 , wherein the edge-emitting semiconductor device is an edge-emitting laser diode chip.

4 . The chip-scale package of claim 1 , wherein the top surface of the chip is an n-side surface, and the bottom surface of the chip is a p-side surface.

5 . The chip-scale package of claim 1 , wherein a front facet of the chip overhangs the bottom submount.

6 . The chip-scale package of claim 1 , wherein the top submount overhangs a front facet of the chip.

7 . The chip-scale package of claim 1 , wherein the top submount is attached to the top surface of the chip with solder, and wherein the bottom submount is attached to the bottom surface of the chip with solder.

8 . The chip-scale package of claim 1 , wherein the top submount and the bottom submount are each formed of a thermally conductive material having a coefficient of thermal expansion (CTE) that is substantially matched to a CTE of the chip.

9 . The chip-scale package of claim 1 , wherein the top submount and the bottom submount are each formed of aluminum nitride, silicon carbide, or a copper-tungsten alloy.

10 . The chip-scale package of claim 1 , wherein the top submount and the bottom submount are each formed of an electrically conductive material or are each provided with wrap-around metallization.

11 . The chip-scale package of claim 1 , wherein the top submount enables an electrical connection to a cathode of the chip, and the bottom submount enables an electrical connection to an anode of the chip.

12 . The chip-scale package of claim 1 , wherein the top-submount area is greater than or equal to the bottom-submount area and corresponds to a package area of the chip-scale package.

13 . The chip-scale package of claim 12 , wherein the package area is less than or equal to about 1 mm 2 .

14 . A semiconductor device assembly comprising:
a chip-scale package comprising:
an edge-emitting semiconductor device chip, having a chip area, comprising a top surface and an opposite bottom surface;
a top submount, having a top-submount area, disposed on the top surface of the chip; and
a bottom submount, having a bottom-submount area, disposed on the bottom surface of the chip;
wherein the top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area; and
a printed circuit board (PCB); wherein the chip-scale package is mounted on the PCB so that the top submount and the bottom submount are each electrically connected to the PCB.

15 . The semiconductor device assembly of claim 14 , wherein the chip-scale package is surface mounted on the PCB.

16 . The semiconductor device assembly of claim 14 , wherein the top submount and the bottom submount are each attached and electrically connected to the PCB with solder or conductive epoxy.

17 . The semiconductor device assembly of claim 16 , wherein the chip-scale package is mounted horizontally on the PCB for emission parallel to the PCB.

18 . The semiconductor device assembly of claim 16 , wherein the chip-scale package is mounted horizontally on the PCB for emission perpendicular to the PCB.

19 . The semiconductor device assembly of claim 14 , wherein the bottom submount is attached and electrically connected to the PCB with solder or conductive epoxy, and the top submount is connected to the PCB through a wire bond or a metal clip.

20 . The semiconductor device assembly of claim 19 , wherein the chip-scale package is mounted vertically on the PCB for emission parallel to the PCB.

Assignees

• Lumentum Operations Llc

Inventors

• Lee Kong Weng
• Wong Vincent V
• Skidmore Jay A
• Du Jihua

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H01S5/02469

  Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC · CPC title

• H01S5/02476 Primary

  Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements · CPC title