Method for manufacturing transistor

Patent metadata

Field	Value
Publication number	US-2016359114-A1
Application number	US-201615244398-A
Country	US
Kind code	A1
Filing date	Aug 23, 2016
Priority date	Mar 7, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

In the manufacturing of transistors, a film substrate on which three or more alignment marks are formed is used, the alignment marks are detected, and a treatment for controlling the expansion and shrinkage of the substrate is carried out once or more by means of at least one of a temperature control of the substrate and a humidity control of the substrate depending on detection results thereof. Therefore, in the manufacturing of transistors in which films are used as substrates, it is possible to form constituent members of transistors such as source electrodes or drain electrodes without pattern deviation regardless of the expansion and shrinkage of substrates attributed to environmental changes.

First claim

What is claimed is:

1 . A method for manufacturing a transistor in which a film is used as a substrate, the method comprising:
using a substrate on which three or more alignment marks are formed; and detecting the alignment marks and carrying out an expansion and shrinkage control treatment for controlling expansion and shrinkage of the substrate once or more by means of at least one of a temperature control of the substrate and a humidity control of the substrate depending on detection results of the alignment marks.

2 . The method for manufacturing a transistor according to claim 1 ,
wherein the manufacturing of the transistor includes at least a step of forming a gate electrode, a step of forming a gate insulating film, a step of forming a semiconductor layer, and a step of forming a source electrode and a drain electrode, and the expansion and shrinkage control treatment is carried out in the middle of or prior to at least one of the step of forming a gate electrode, the step of forming a gate insulating film, the step of forming a semiconductor layer, and the step of forming a source electrode and a drain electrode.

3 . The method for manufacturing a transistor according to claim 1 ,
wherein a degree of deviation of the alignment marks is detected from the detection results of the alignment marks, and at least one of the temperature control of the substrate and the humidity control of the substrate is carried out on the basis of the degree of deviation of the alignment marks and at least one of a linear expansion coefficient and a hygroscopic expansion coefficient of the substrate.

4 . The method for manufacturing a transistor according to claim 2 ,
wherein a degree of deviation of the alignment marks is detected from the detection results of the alignment marks, and at least one of the temperature control of the substrate and the humidity control of the substrate is carried out on the basis of the degree of deviation of the alignment marks and at least one of a linear expansion coefficient and a hygroscopic expansion coefficient of the substrate.

5 . The method for manufacturing a transistor according to claim 3 ,
wherein the transistor is manufactured by fixing the substrate to a carrier, at least one of the linear expansion coefficient and hygroscopic expansion coefficient of the substrate is ascertained in a state in which the substrate is fixed to the carrier, and at least one of the temperature control of the substrate and the humidity control of the substrate is carried out using the ascertained information.

6 . The method for manufacturing a transistor according to claim 4 ,
wherein the transistor is manufactured by fixing the substrate to a carrier, at least one of the linear expansion coefficient and hygroscopic expansion coefficient of the substrate is ascertained in a state in which the substrate is fixed to the carrier, and at least one of the temperature control of the substrate and the humidity control of the substrate is carried out using the ascertained information.

7 . The method for manufacturing a transistor according to claim 1 ,
wherein, in a state in which at least one of the temperature and humidity of the substrate obtained by the expansion and shrinkage control treatment is maintained, pattern exposure in which a printing method or a photo mask is used is carried out, thereby carrying out pattern formation in the manufacturing of the transistor.

8 . The method for manufacturing a transistor according to claim 2 ,
wherein, in a state in which at least one of the temperature and humidity of the substrate obtained by the expansion and shrinkage control treatment is maintained, pattern exposure in which a printing method or a photo mask is used is carried out, thereby carrying out pattern formation in the manufacturing of the transistor.

9 . The method for manufacturing a transistor according to claim 3 ,
wherein, in a state in which at least one of the temperature and humidity of the substrate obtained by the expansion and shrinkage control treatment is maintained, pattern exposure in which a printing method or a photo mask is used is carried out, thereby carrying out pattern formation in the manufacturing of the transistor.

10 . The method for manufacturing a transistor according to claim 4 ,
wherein, in a state in which at least one of the temperature and humidity of the substrate obtained by the expansion and shrinkage control treatment is maintained, pattern exposure in which a printing method or a photo mask is used is carried out, thereby carrying out pattern formation in the manufacturing of the transistor.

11 . The method for manufacturing a transistor according to claim 5 ,
wherein, in a state in which at least one of the temperature and humidity of the substrate obtained by the expansion and shrinkage control treatment is maintained, pattern exposure in which a printing method or a photo mask is used is carried out, thereby carrying out pattern formation in the manufacturing of the transistor.

12 . The method for manufacturing a transistor according to claim 6 ,
wherein, in a state in which at least one of the temperature and humidity of the substrate obtained by the expansion and shrinkage control treatment is maintained, pattern exposure in which a printing method or a photo mask is used is carried out, thereby carrying out pattern formation in the manufacturing of the transistor.

13 . The method for manufacturing a transistor according to claim 1 ,
wherein the expansion and shrinkage control treatment is a humidity control, and the expansion and shrinkage control treatment is carried out by blowing gas having a controlled humidity toward the substrate.

14 . The method for manufacturing a transistor according to claim 2 ,
wherein the expansion and shrinkage control treatment is a humidity control, and the expansion and shrinkage control treatment is carried out by blowing gas having a controlled humidity toward the substrate.

15 . The method for manufacturing a transistor according to claim 1 ,
wherein the alignment marks are detected while transporting a long substrate in a longitudinal direction, the expansion and shrinkage control treatment is carried out on the downstream side of a detection position of the alignment marks, and pattern formation is carried out on the downstream side of the expansion and shrinkage control treatment in the manufacturing of the transistor.

16 . The method for manufacturing a transistor according to claim 1 ,
wherein the substrate is a gas barrier film obtained by forming a gas barrier membrane on a support, and the gas barrier membrane is obtained by alternately laminating one or more of organic layers and inorganic layers.

17 . The method for manufacturing a transistor according to claim 16 ,
wherein the inorganic layer is a silicon nitride film.

18 . The method for manufacturing a transistor according to claim 1 , further comprising:
a step of forming an organic semiconductor layer.

19 . The method for manufacturing a transistor according to claim 1 ,
wherein a heat treatment of the substrate is carried out prior to the expansion and shrinkage control treatment carried out for the first time.

20 . The method for manufacturing a transistor according to claim 1 ,
wherein a step of forming the alignment marks is included, and the alignment marks are formed when patterning for a lowermost layer is carried out in the manufacturing of the transistor.

Assignees

• Fujifilm Corp

Inventors

• Nakamura Seigo

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title