Solid state photomultiplier

Patent metadata

Field	Value
Publication number	US-2016358957-A1
Application number	US-201615077006-A
Country	US
Kind code	A1
Filing date	Mar 22, 2016
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include an epitaxial layer, a high voltage region formed in the epitaxial layer, a low voltage region formed in the epitaxial layer, and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

First claim

1 . A solid state photomultiplier, comprising:
an epitaxial layer; a high voltage region formed in the epitaxial layer; a low voltage region formed in the epitaxial layer; and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

2 . The solid state photomultiplier of claim 1 , wherein the intermediate region and the low voltage region comprise substantially similar active and passive devices.

3 . The solid state photomultiplier of claim 1 , wherein the solid state photomultiplier does not utilize high voltage transistors to perform at least one of a quenching or resetting of the solid state photomultiplier.

4 . The solid state photomultiplier of claim 1 , wherein each of the low voltage region and intermediate region comprises:
a deep well formed in the epitaxial layer; and a plurality of wells formed in the deep well, wherein the deep well comprises one of an n-type or p-type dopant and wherein at least one of the plurality of wells comprises an n-type or p-type dopant opposite that of the deep well.

5 . The solid state photomultiplier of claim 4 , wherein the deep well and plurality of wells formed in the deep well of the intermediate region are self-biased.

6 . The solid state photomultiplier of claim 4 , wherein the deep well and plurality of wells formed in the deep well of the intermediate region has a bias such that a voltage difference across any two terminals of a transistor in the intermediate region is less than a highest positive voltage of the low voltage region.

7 . The solid state photomultiplier of claim 4 , wherein the high voltage region comprises:
a deep well formed in the epitaxial layer; and a well disposed above and at least partially overlapping the deep well, wherein the deep well comprises one of an n-type or p-type dopant and the well disposed above the deep well comprises an n-type or p-type dopant opposite that of the deep well, and wherein the well disposed above the deep well is electically coupled to the deep well of the intermediate region.

8 . The solid state photomultiplier of claim 4 , wherein each of the low voltage region and intermediate region comprises at least one gate structure formed above the deep well to form at least one transistor in the low voltage region and at least one transistor in the intermediate voltage region.

9 . The solid state photomultiplier of clam 8 , wherein the at least one transistor formed in the intermediate region comprises an electrical coupling between a gate and a drain and between a source and a substrate of the transistor.

10 . The solid state photomultiplier of claim 1 , wherein the solid state photomultiplier is a silicon photomultiplier.

11 . A detector for an imaging system, comprising:
a detector assembly having a plurality of solid state photomultipliers coupled to readout electronics, wherein each of the solid state photomultipliers comprises:
an epitaxial layer;
a high voltage region formed in the epitaxial layer;
a low voltage region formed in the epitaxial layer; and
an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

12 . The detector of claim 11 , wherein the intermediate region and the low voltage region comprise substantially similar active and passive devices.

13 . The detector of claim 11 , wherein the solid state photomultiplier does not utilize high voltage transistors to perform at least one of a quenching or resetting of the solid state photomultiplier.

14 . The detector of claim 11 , wherein each of the low voltage region and intermediate region comprises:
a deep well formed in the epitaxial layer; and a plurality of wells formed in the deep well, wherein the deep well comprises one of an n-type or p-type dopant and wherein at least one of the plurality of wells comprises an n-type or p-type dopant opposite that of the deep well.

15 . The detector of claim 14 , wherein the deep well and plurality of wells formed in the deep well of the intermediate region are self-biased.

16 . The detector of claim 14 , wherein the deep well and plurality of wells formed in the deep well of the intermediate region has a bias such that a voltage difference across any two terminals of a transistor in the intermediate region is less than a highest positive voltage of the low voltage region.

17 . The detector of claim 14 , wherein the high voltage region comprises:
a deep well formed in the epitaxial layer; and a well disposed above and at least partially overlapping the deep well, wherein the deep well comprises one of an n-type or p-type dopant and the well disposed above the deep well comprises an n-type or p-type dopant opposite that of the deep well, and wherein the well disposed above the deep well is electically coupled to the deep well of the intermediate region.

18 . The detector of claim 14 , wherein each of the low voltage region and intermediate region comprises at least one gate structure formed above the deep well to form at least one transistor in the low voltage region and at least one transistor in the intermediate voltage region.

19 . The detector of claim 18 , wherein the at least one transistor formed in the intermediate region comprises an electrical coupling between a gate and a drain and between a source and a substrate of the transistor.

20 . The detector of claim 11 , wherein the solid state photomultiplier is a silicon photomultiplier.

Assignees

• Gen Electric

Inventors

• Guo Jianjun
• Dolinsky Sergei Ivanovich
• Short Jonathan David

Classifications

• H01L31/035272

  Electricity · mapped topic

• H01L27/14612 Primary

  Electricity · mapped topic

• H10F77/14

  Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies · CPC title

• H10F39/1898

  Indirect radiation image sensors, e.g. using luminescent members · CPC title

• H10F39/8037 Primary

  the integrated elements comprising a transistor · CPC title