Silicon germanium-on-insulator formation by thermal mixing

Patent metadata

Field	Value
Publication number	US-2016358774-A1
Application number	US-201615237235-A
Country	US
Kind code	A1
Filing date	Aug 15, 2016
Priority date	Feb 12, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.

First claim

What is claimed as new is:

1 . A method of forming a silicon germanium-on-insulator (SGOI) material, said method comprising:
providing a structure comprising, from bottom to top, a silicon-on-insulator substrate and a germanium layer; and converting said structure into a silicon germanium-on-insulator material by annealing, wherein during said annealing silicon atoms from a silicon layer of said silicon-on-insulator substrate intermix with germanium atoms in said germanium layer to form a silicon germanium layer.

2 . The method of claim 1 , wherein said silicon layer of said silicon-on-insulator substrate is single crystalline.

3 . The method of claim 1 , wherein said germanium layer is continuously present on a topmost surface of said silicon layer of said silicon-on-insulator substrate.

4 . The method of claim 1 , wherein said germanium layer has an epitaxial relationship with said silicon layer of said silicon-on-insulator substrate.

5 . The method of claim 1 , wherein said germanium layer is hydrogenated.

6 . The method of claim 1 , wherein said germanium layer is completely consumed by said annealing.

7 . The method of claim 1 , wherein said germanium layer is partially consumed by said annealing.

8 . The method of claim 7 , further comprising removing a remaining portion of said germanium layer.

9 . The method of claim 1 , further comprising forming a dielectric material on a surface of said germanium layer prior to said converting.

10 . The method of claim 1 , further comprising forming an amorphous region at an interface between said germanium layer and said silicon layer of said silicon-on-insulator substrate prior to said converting.

11 . The method of claim 10 , wherein said forming said amorphous region comprises ion implanting an amorphizing ion into said structure prior to said annealing.

12 . The method of claim 11 , wherein said amorphizing ion comprises Si or Ge.

13 . The method of claim 11 , wherein said ion implanting is performed at or below room temperature.

14 . The method of claim 10 , wherein said amorphous region is a continuously present between said germanium layer and said silicon layer of said silicon-on-insulator substrate.

15 . The method of claim 10 , wherein said annealing crystallizes said amorphous region.

16 . The method of claim 1 , wherein said annealing is a thermal anneal performed in hydrogen.

17 . The method of claim 1 , wherein said silicon germanium layer has a germanium content from greater than 50 atomic percent germanium to 90 atomic percent germanium.

Assignees

• IBM

Inventors

• Bedell Stephen W
• De Souza Joel P
• Kim Jeehwan
• Sadana Devendra K

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/50

  Alloying conductive materials with semiconductor bodies · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P32/16

  between a solid phase and a liquid phase · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title