Scan driving circuit

Patent metadata

Field	Value
Publication number	US-2016358564-A1
Application number	US-201514777748-A
Country	US
Kind code	A1
Filing date	Jul 17, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A scan driving circuit is provided for driving scan lines which are connected in series, including a pull-down controlling module, a pull-down module, a reset-controlling module, a resetting module, a downward-transmitting module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source. The entire structure of the scan driving circuit is simple, and energy consumption is reduced.

First claim

What is claimed is:

1 . A scan driving circuit for driving scan lines connected in series, comprising:
a pull-down controlling module for receiving a scan signal from a former stage and generating a scan voltage signal having a low voltage level with respect to a scan line according to the scan signal from the former stage; a pull-down module for pulling down the scan signal with respect to the scan line according to the scan voltage signal; a reset-controlling module for receiving a clock signal from a next stage and generating a reset signal with respect to the scan line according to the clock signal from the next stage; a resetting module for pulling up the scan signal with respect to the scan line according to the reset signal; a downward-transmitting module for generating and transmitting a clock signal of a current stage and a pull-down controlling signal of the current stage according to the scan signal of the scan line; a first bootstrap capacitor for generating the scan voltage signal either having the low voltage level or a high voltage level of the scan line; a constant low voltage level source for providing a low voltage level signal; and a constant high voltage level source for providing a high voltage level signal, wherein either P-type metal-oxide semiconductor transistors or N-type metal-oxide semiconductor transistors are utilized in the scan driving circuit to control the pull-down controlling module, the pull-down module, the reset-controlling module, and the resetting module; the pull-down controlling module is also used for receiving a scan signal from the next stage and generating the scan voltage signal having the low voltage level with respect to the scan line according to the scan signal from the next stage; and the reset-controlling module is also used for receiving a clock signal from the former stage and generating the reset signal with respect to the scan line according to the clock signal from the former stage.

2 . The scan driving circuit as claimed in claim 1 , wherein the pull-down controlling module comprises a first transistor; a scan signal having a low voltage level is inputted into a control end of the first transistor; the scan signal from the former stage is inputted into an input end of the first transistor; and an output end of the first transistor is connected with the pull-down module.

3 . The scan driving circuit as claimed in claim 2 , wherein the pull-down module comprises a second transistor; a control end of the second transistor is connected with the output end of the first transistor of the pull-down controlling module; an input end of the second transistor is connected with the output end of the first transistor of the pull-down controlling module; and the scan voltage signal having the low voltage level of the scan line is outputted by an output end of the second transistor.

4 . The scan driving circuit as claimed in claim 3 , wherein the reset-controlling module comprises a third transistor; the scan signal having the low voltage level is inputted into a control end of the third transistor; the clock signal from the next stage is inputted into an input end of the third transistor; and the reset signal of the scan line is outputted by an output end of the third transistor.

5 . The scan driving circuit as claimed in claim 4 , wherein the resetting module comprises a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
a control end of the fourth transistor is connected with the output end of the third transistor; an input end of the fourth transistor is connected with the constant low voltage level source; and an output end of the fourth transistor is respectively connected with a control end of the fifth transistor, a control end of the seventh transistor, and an output end of the sixth transistor; an input end of the fifth transistor is connected with the constant high voltage level source; and an output end of the fifth transistor is connected with the output end of the second transistor; a control end of the sixth transistor is connected with the output end of the second transistor; and an input end of the sixth transistor is connected with the constant high voltage level source; and an input end of the seventh transistor is connected with the constant high voltage level source; and the scan signal of the current stage of the scan line is outputted by an output end of the seventh transistor.

6 . The scan driving circuit as claimed in claim 5 , wherein the downward-transmitting module comprises an eighth transistor; a control end of the eighth transistor is connected with the output end of the second transistor; an input end of the eighth transistor is connected with the output end of the seventh transistor; and the clock signal of current stage is outputted by an output end of the eighth transistor.

7 . The scan driving circuit as claimed in claim 6 , wherein the downward-transmitting module further comprises a tenth transistor; a control end of the tenth transistor is connected with the output end of the second transistor; an input end of the tenth transistor is connected with the output end of the eighth transistor; and the pull-down controlling signal of the current stage is outputted by an output end of the tenth transistor.

8 . The scan driving circuit as claimed in claim 7 , wherein an end of the first bootstrap capacitor is connected with the output end of the second transistor; and another end of the first bootstrap capacitor is connected with the output end of the seventh transistor.

9 . The scan driving circuit as claimed in claim 8 , wherein the scan driving circuit further comprises an electric leakage-preventive module; the electric leakage-preventive module comprises a ninth transistor; a control end of the ninth transistor is connected with the constant low voltage level source; an input end of the ninth transistor is connected with the output end of the second transistor; and an output end of the ninth transistor is connected with the output end of the seventh transistor via the first bootstrap capacitor.

10 . The scan driving circuit as claimed in claim 9 , wherein the resetting module further comprises a second bootstrap capacitor; an end of the second bootstrap capacitor is connected with the constant high voltage level source; and another end of the second bootstrap capacitor is connected with the output end of the fourth transistor.

11 . A scan driving circuit for driving scan lines connected in series, comprising:
a pull-down controlling module for receiving a scan signal from a former stage and generating a scan voltage signal having a low voltage level with respect to a scan line according to the scan signal from the former stage; a pull-down module for pulling down the scan signal with respect to the scan line according to the scan voltage signal; a reset-controlling module for receiving a clock signal from a next stage and generating a reset signal with respect to the scan line according to the clock signal from the next stage; a resetting module for pulling up the scan signal with respect to the scan Brie according to the reset signal; a downward-transmitting module for generating and transmitting a clock signal of a current stage and a pull-down controlling signal of the current stage according to the scan signal of the scan line; a first bootstrap capacitor for generating the scan voltage signal either having the low voltage level or a high voltage level of the scan line; a constant low voltage level source for providing a low voltage level signal; and a constant high voltage level source for providing a high voltage level signal.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Xiao Juncheng
• Zhao Mang
• Yan Yao

Classifications

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title