Array substrate and manufacturing and repairing method thereof, display device

Patent metadata

Field	Value
Publication number	US-9502438-B2
Application number	US-201414426003-A
Country	US
Kind code	B2
Filing date	May 14, 2014
Priority date	Dec 31, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

An array substrate and manufacturing thereof are provided. The array substrate comprises gate lines, first data lines, second data lines and N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines. A repairing line for each column of the pixel units is provided for a region at which at least one row of pixel units are located. Projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line.

First claim

What is claimed is:

1. An array substrate, comprising:
gate lines;
first data lines;
second data lines; and
N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines, where N is a total number of rows of the pixel units, and M is a total number of columns of the pixel units;
the first data lines are configured to drive odd numbered pixel units in a same column of the pixel units, the second data lines are configured to drive even numbered pixel units in the same column of the pixel units; and
a repairing line for each column of the pixel units is provided in a region at which at least one row of the pixel units are located;
wherein projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line, and wherein the pixel units each comprise a pixel electrode; and the repairing line and the pixel electrode are formed simultaneously and located in a same layer of the array substrate.

2. An array substrate, comprising:
gate lines;
first data lines;
second data lines; and
N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines, where N is a total number of rows of the pixel units, and M is a total number of columns of the pixel units;
the first data lines are configured to drive odd numbered pixel units in a same column of the pixel units, the second data lines are configured to drive even numbered pixel units in the same column of the pixel units; and
a repairing line for each column of the pixel units is provided in a region at which at least one row of the pixel units are located;
wherein projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line, and wherein the repairing line is a transparent electrode film.

3. The array substrate according to claim 2 , wherein the two ends of the repairing line respectively extend beyond regions at which the first data line and the second data line are located, and are perpendicular to the first data line and the second data line.

4. The array substrate according to claim 3 , wherein the repairing line is located at a non-display region of the pixel unit.

5. The array substrate according to claim 2 , wherein the repairing line and the gate lines are formed simultaneously and are located in a same layer of the array substrate.

6. The array substrate according to claim 1 , wherein the repairing line is located in a middle area of a region of the corresponding pixel unit.

7. The array substrate according to claim 1 , wherein for an i th column of the pixel units, the repairing line is provided in a region at which the pixel units are located in every n i rows, wherein 0≦n i ≦N−1, i=1, 2, . . . , M.

8. The array substrate according to claim 7 , wherein the number of n i is 0, 1, 2, 3, 4 or 5.

9. A method of manufacturing an array substrate, comprising:
forming a pattern comprising gate lines, first data lines, second data lines and N×M pixel units defined by the gate lines, the first data lines and the second data lines, where N is a total number of rows of the pixel units, M is a total number of columns of the pixel units, the first data lines are configured to drive odd numbered pixel units in a same column of the pixel units, and the second data lines are configured to drive even numbered pixel units in the same column of pixel units; and
in each column of pixel units, forming a pattern of a repairing line in a region at which at least one row of pixel units are located so that projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of the pixel units are located, and the repairing line is isolated from the first data line and the second data line.

10. The method of manufacturing the array substrate according to claim 9 , further comprising forming a pattern of a pixel electrode in each pixel unit, wherein the pattern of the repairing line and the pattern of the pixel electrode are formed simultaneously in a same layer of the array substrate.

11. The method of manufacturing the array substrate according to claim 9 , wherein the repairing line is formed of a transparent electrode film.

12. The method of manufacturing the array substrate according to claim 11 , wherein two ends of the repairing line respectively extend beyond the regions at which the first data line and the second data line are located, and are perpendicular to the first data line and the second data line.

13. The method of manufacturing the array substrate according to claim 12 , wherein the repairing line is located in a non-display region of the corresponding pixel unit.

14. The method of manufacturing the array substrate according to claim 9 , wherein the pattern of the repairing line and a pattern of the gate lines are formed simultaneously in a same layer of the array substrate.

15. The method of manufacturing the array substrate according to claim 9 , wherein the repairing line is located in a middle area of a region of the corresponding pixel unit.

16. The method of manufacturing the array substrate according to claim 9 , wherein for an i th column of pixel units, the repairing line is provided in a region at which the pixel units are located in every n i rows, where 0≦n i ≦N−1, i=1, 2, . . . , M.

17. The method of manufacturing the array substrate according to claim 16 , wherein the number of n i is 0, 1, 2, 3, 4 or 5.

18. A display device comprising the array substrate according to claim 1 .

19. The array substrate according to claim 1 , wherein the repairing line is a transparent electrode film.

20. The array substrate according to claim 1 , wherein the two ends of the repairing line respectively extend beyond regions at which the first data line and the second data line are located, and are perpendicular to the first data line and the second data line.

21. The array substrate according to claim 1 , wherein the repairing line is located at a non-display region of the pixel unit.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Kim Jaikwang
• Yoon Yongjun

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L2924/0002

  Electricity · mapped topic