Selective error coding

Patent metadata

Field	Value
Publication number	US-2016357629-A1
Application number	US-201514835790-A
Country	US
Kind code	A1
Filing date	Aug 26, 2015
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

First claim

What is claimed is:

1 . A method of performing selective error coding in memory management of a memory device, the method comprising:
performing, using a processor, a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place, the chip mark indicating all addresses of the memory device as bad; localizing hard errors of the memory device, using the processor, based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process; determining an extent of the hard errors based on the localizing; and preventing placement of the chip mark or removing the chip mark to resume memory use of the memory device after de-allocating one or more ranges of addresses of the memory of the memory device based on a result of the determining the extent of the hard errors.

2 . The method according to claim 1 , wherein the performing the process of detecting and correcting the memory errors includes a first scrubbing process to correct soft errors.

3 . The method according to claim 1 , wherein the second process of detecting the memory errors includes a second scrubbing process.

4 . The method according to claim 3 , wherein the localizing the hard errors includes determining a number of sub-regions of the memory that are bad.

5 . The method according to claim 4 , wherein the determining the number of sub-regions of the memory that are bad includes determining the number of sub-regions of the memory with greater than a first threshold number of addresses that are bad.

6 . The method according to claim 4 , wherein the determining the extent of the hard errors includes determining whether the number of sub-regions of the memory that are bad is below a second threshold.

7 . The method according to claim 6 , wherein the preventing the placement of the chip mark or the removing the chip mark is done when the number of sub-regions of the memory that are bad is below the second threshold.

8 . The method according to claim 6 , wherein placing the chip mark or maintaining the chip mark is done when the number of sub-regions of the memory that are bad is above the second threshold.

Assignees

• IBM

Inventors

• Chinnakkonda Vidyapoornachary Diyanesh Babu
• Dell Timothy J
• Gollub Marc A
• Lingambudi Anil B

Classifications

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title