Planar cavity mems and related structures, methods of manufacture and design structures

Patent metadata

Field	Value
Publication number	US-2016355392-A1
Application number	US-201615238854-A
Country	US
Kind code	A1
Filing date	Aug 17, 2016
Priority date	Jun 25, 2010
Publication date	Dec 8, 2016
Grant date	—

Abstract

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

First claim

What is claimed:

1 . A method in a computer-aided design system for generating a functional design model of a MEMS, the method comprising:
generating a functional representation of a wiring layer to form at least one fixed plate; generating a functional representation of an insulator layer over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of aluminum silicide during a subsequent sacrificial material deposition step; generating a functional representation of at least one upper MEMS beam over the at least one fixed plate; and generating a functional representation of venting or stripping of the sacrificial material to form at least a lower cavity, wherein the generating a functional representation of an insulator layer over the at least one fixed plate comprises a functional representation of a conformal oxidization barrier layer comprising at least one of Al 2 O 3 and Ta 2 O 5 .

2 . The method of claim 1 , wherein the at least one fixed plate is a patterned wiring layer.

3 . The method of claim 1 , wherein the insulating layer has a tapered profile.

4 . The method of claim 3 , wherein the tapered profile is tapered to a 45 degree angle.

5 . The method of claim 1 , wherein the insulating layer has a double tapered profile.

6 . The method of claim 1 , wherein the conformal oxidation barrier layer comprises a combination of Al 2 O 3 and Ta 2 O 5 .

7 . The method of claim 1 , wherein the at least one fixed plate contains aluminum.

8 . The method of claim 1 , wherein the insulator layer also covers sidewall surfaces of the at least one fixed plate.

9 . The method of claim 1 , further comprising generating a functional representation of a TiN/TiAl 3 layer between the at least one fixed plate and the insulator layer.

10 . The method of claim 1 , wherein the insulator layer over the at least one fixed plate acts to block reaction, alloying, or interdiffusion of material of the at least one fixed plate and the sacrificial material.

11 . The method of claim 1 , wherein the sacrificial material comprises silicon.

Assignees

• IBM

Inventors

• Stamper Anthony K
• Twombly John G

Classifications

• Y10T29/435

  Solid dielectric type · CPC title

• Y10T29/42

  Piezoelectric device making · CPC title

• Y10T29/49105

  Switch making · CPC title

• B81C2201/0167

  by adding further layers of materials having complementary strains, i.e. compressive or tensile strain · CPC title

• Y10T29/49002

  Electrical device making · CPC title