Silicon carbide semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-2016351667-A1
Application number	US-201515114009-A
Country	US
Kind code	A1
Filing date	Jul 22, 2015
Priority date	Aug 29, 2014
Publication date	Dec 1, 2016
Grant date	—

Abstract

A silicon carbide epitaxial layer includes: a first impurity region; a second impurity region; and a third impurity region. A gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region. A groove portion is formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm.

First claim

1 . A silicon carbide semiconductor device comprising:
a silicon carbide epitaxial layer including a first impurity region, a second impurity region, and a third impurity region, the first impurity region having a first conductivity type, the second impurity region being provided in contact with the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being separated from the first impurity region by the second impurity region, the third impurity region having the first conductivity type; and a gate insulating film in contact with the first impurity region, the second impurity region, and the third impurity region, a groove portion being formed in a surface of the first impurity region, the surface being in contact with the gate insulating film, the groove portion extending in one direction along the surface, a width of the groove portion in the one direction being twice or more as large as a width of the groove portion in a direction perpendicular to the one direction, a maximum depth of the groove portion from the surface being not more than 10 nm, the groove portion including a first groove portion and a second groove portion connected to the first groove portion, the first groove portion being formed in one end portion of the groove portion in the one direction, the second groove portion extending in the one direction from the first groove portion to the other end portion opposite to the one end portion, a depth of the second groove portion from the surface being smaller than a maximum depth of the first groove portion.

2 . The silicon carbide semiconductor device according to claim 1 , wherein a width of the surface of the first impurity region in a direction along a direction parallel to the surface of the first impurity region is not less than 1.5 μm and not more than 3.5 μm.

3 . The silicon carbide semiconductor device according to claim 1 , wherein a thickness of the gate insulating film in a direction perpendicular to the surface of the first impurity region is not less than 40 nm and not more than 100 nm.

4 . The silicon carbide semiconductor device according to claim 1 , wherein a density of nitrogen atoms is not less than 10 18 cm −1 in a boundary region between the gate insulating film and the first impurity region.

5 . (canceled)

6 . The silicon carbide semiconductor device according to claim 1 , wherein the gate insulating film is provided on the first groove portion.

7 . (canceled)

8 . (canceled)

9 . (canceled)

Assignees

• Sumitomo Electric Industries

Inventors

• Wada Keiji
• Nishiguchi Taro
• Hiyoshi Toru
• Horii Taku
• Uchida Kosuke

Classifications

• H10P50/00 Primary

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2904

  Silicon carbide · CPC title