Silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate

Patent metadata

Field	Value
Publication number	US-2016197155-A1
Application number	US-201514957243-A
Country	US
Kind code	A1
Filing date	Dec 2, 2015
Priority date	Jan 6, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A silicon carbide substrate has a silicon carbide epitaxial layer. The silicon carbide epitaxial layer has a first main surface and a second main surface opposite to the first main surface. The silicon carbide epitaxial layer has a thickness of not less than 50 μm in a direction perpendicular to the second main surface. Z 1/2 centers are in the silicon carbide epitaxial layer at a density of not more than 1×10 12 cm −3 . A pit has a maximum depth of not more than 5 nm, the pit originating from a threading dislocation or a basal plane dislocation and having an opening at the second main surface.

First claim

What is claimed is:

1 . A silicon carbide substrate comprising a silicon carbide epitaxial layer having a first main surface and a second main surface opposite to said first main surface,
said silicon carbide epitaxial layer having a thickness of not less than 50 μm in a direction perpendicular to said second main surface, Z 1/2 centers being in said silicon carbide epitaxial layer at a density of not more than 1×10 12 cm −3 , a pit having a maximum depth of not more than 5 nm, said pit originating from a threading dislocation or a basal plane dislocation and having an opening at said second main surface.

2 . The silicon carbide substrate according to claim 1 , wherein
said silicon carbide epitaxial layer includes an impurity capable of providing one of p type and n type, and said impurity has a concentration of not more than 1×10 15 cm −3 .

3 . The silicon carbide substrate according to claim 1 , wherein a carrier lifetime is not less than 1 microsecond.

4 . A silicon carbide semiconductor device comprising:
the silicon carbide substrate recited in claim 1 ; a gate insulating film provided on said second main surface; and a gate electrode provided on said gate insulating film, the silicon carbide semiconductor device having a breakdown voltage of not less than 6.5 kV.

5 . A method for manufacturing a silicon carbide substrate comprising steps of:
preparing a silicon carbide epitaxial substrate including a silicon carbide single crystal substrate on which a silicon carbide epitaxial layer is provided, said silicon carbide epitaxial layer having a first main surface and a second main surface, said first main surface being in contact with said silicon carbide single crystal substrate, said second main surface being opposite to said first main surface; forming an oxide film in contact with said silicon carbide epitaxial layer by oxidizing said second main surface; exposing a third main surface of said silicon carbide epitaxial layer by removing said oxide film from said silicon carbide epitaxial layer; annealing said silicon carbide epitaxial substrate after the step of exposing said third main surface; and exposing a fourth main surface of said silicon carbide epitaxial layer by removing a surface layer including said third main surface after the step of annealing said silicon carbide epitaxial substrate, in the step of forming said oxide film, a pit being formed in said silicon carbide epitaxial layer, said pit originating from a threading dislocation or a basal plane dislocation and having a depth larger than 5 nm, in the step of exposing said fourth main surface, said pit having a maximum depth of not more than 5 nm.

6 . The method for manufacturing the silicon carbide substrate according to claim 5 , wherein in the step of exposing said fourth main surface, chemical mechanical polishing is performed onto said third main surface.

7 . The method for manufacturing the silicon carbide substrate according to claim 5 , wherein said oxide film has a thickness of not less than 100 μm in a direction perpendicular to said first main surface.

8 . The method for manufacturing the silicon carbide substrate according to claim 5 , wherein after the step of annealing said silicon carbide epitaxial substrate, Z 1/2 centers are in said silicon carbide epitaxial layer at a density of not more than 1×10 12 cm −3 .

9 . The method for manufacturing the silicon carbide substrate according to claim 5 , further comprising a step of forming a carbon film on said third main surface after the step of removing said oxide film and before the step of annealing said silicon carbide epitaxial substrate, wherein
in the step of annealing said silicon carbide epitaxial substrate, said silicon carbide epitaxial substrate is annealed with said carbon film being provided on said third main surface.

10 . The method for manufacturing the silicon carbide substrate according to claim 5 , wherein in the step of annealing said silicon carbide epitaxial substrate, said silicon carbide epitaxial substrate is annealed at not less than 1400° C. and not more than 2000° C.

Assignees

• Sumitomo Electric Industries

Inventors

• Hiyoshi Toru

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P90/12 Primary

  Preparing bulk and homogeneous wafers · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P50/642

  Chemical etching · CPC title