Floating Point Computation Apparatus and Method

Patent metadata

Field	Value
Publication number	US-2016350073-A1
Application number	US-201514726246-A
Country	US
Kind code	A1
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

First claim

What is claimed is:

1 . An apparatus comprising:
an input block configured to receive a first N-bit unsigned number and a second N-bit unsigned number, wherein the input block comprises N propagate and generate cells; a plurality of calculation cells arranged in rows and columns, wherein the number of the columns is equal to N and the number of the rows is equal to log 2 (N) wherein each row has N cells and has an index ri, and wherein a variable d is equal to 2 ri , and wherein each calculation cell has three groups of inputs connected to three cells in a preceding row, and wherein:
a first group of inputs are connected to outputs of a first calculation cell in the preceding row and vertically aligned with the calculation cell;
a second group of inputs are connected to outputs of a second calculation cell that is d cells away from the first calculation cell; and
a third group of inputs are connected to outputs of a third calculation cell that is 2d cells away from the first calculation cell; and
an output block comprising a plurality of XOR gates.

2 . The apparatus of claim 1 , wherein:
the propagate and generate cell comprises an AND gate and a XOR gate, wherein:
a first input of the AND gate is connected to a first input of the XOR gate; and
a second input of the AND gate is connected to a second input of the XOR gate.

3 . The apparatus of claim 1 , wherein:
the calculation cell comprises a propagate and shift (PS) unit and a generate and shift (GS) unit.

4 . The apparatus of claim 3 , wherein:
the PS unit comprises an NOT gate, a first AND gate, a second AND gate and an OR gate, and wherein:
the NOT gate is configured to receive a control signal;
the first AND gate has a first input connected to an output of the NOT gate, a second input configured to receive an output signal from a PS unit of the first calculation cell and a third input configured to receive an output signal from a PS unit of the second calculation cell;
the second AND gate has a first input configured to receive the control signal, a second input configured to receive the output signal from the PS unit of the second calculation cell and a third input configured to receive an output signal from a PS unit of the third calculation cell; and
the OR gate has a first input connected to an output of the first AND gate and a second input connected to an output of the second AND gate.

5 . The apparatus of claim 3 , wherein:
the GS unit comprises an NOT gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first NOR gate, a second NOR gate and a NAND gate, and wherein:
the first NOR gate is connected to outputs of the first AND gate and the second AND gate;
the second NOR gate is connected to outputs of the third AND gate and the fourth AND gate; and
the NAND gate is connected to outputs of the first NOR gate and the second NOR gate.

6 . The apparatus of claim 5 , wherein:
the NOT gate is configured to receive a control signal; the first AND gate has a first input connected to an output of the NOT gate, a second input configured to receive an output signal from a PS unit of the first calculation cell and a third input configured to receive an output signal from a GS unit of the second calculation cell; the second AND gate has a first input connected to the output of the NOT gate and a second input configured to receive an output signal from a GS unit of the first calculation cell; the third AND gate has a first input configured to receive the control signal, a second input configured to receive an output signal from a PS unit of the second calculation cell and a third input configured to receive an output signal from a GS unit of the third calculation cell; and the fourth AND gate has a first input configured to receive the control signal and a second input configured to receive the output signal from the GS unit of the second calculation cell.

7 . The apparatus of claim 1 , further comprising:
a barrel shifter configured to receive a control signal and a binary number, and shift the binary number to the left by a number of bits indicated by the control signal.

8 . The apparatus of claim 7 , wherein:
a XOR gate of the output block has a first input connected to an output of a GS unit of a last row of the calculation cells and a second input connected to a corresponding bit of an output of the barrel shifter.

9 . The apparatus of claim 7 , wherein:
the output of the barrel shifter has (N+1) bits.

10 . The apparatus of claim 1 , wherein:
the plurality of calculation cells are configured such that an addition/subtraction operation and a shifting process are applied in parallel to the first N-bit unsigned number and the second N-bit unsigned number.

11 . A system comprising:
an input block configured to receive a first N-bit unsigned number, a second N-bit unsigned number and a control signal, wherein the input block comprises N propagate and generate cells; a plurality of calculation cells arranged in rows and columns and coupled to the input block, wherein the calculation cells are configured to perform an add operation and a shifting operation based upon the control signal, and the add operation and the shifting operation are applied in parallel to the first N-bit unsigned number and the second N-bit unsigned number; and an output block comprising a plurality of XOR gates coupled to a last row of the plurality of calculation cells.

12 . The system of claim 11 , wherein:
the number of the columns is equal to N; and the number of the rows is equal to log 2 (N) .

13 . The system of claim 11 , wherein:
each row has N cells and has an index ri, and wherein a variable d is equal to 2 ri , and wherein each calculation cell has three groups of inputs connected to three cells in a preceding row, and wherein:
a first group of inputs are connected to outputs of a first calculation cell in the preceding row and vertically aligned with the calculation cell;
a second group of inputs are connected to outputs of a second calculation cell that is d cells away from the first calculation cell; and
a third group of inputs are connected to outputs of a third calculation cell that is 2d cells away from the first calculation cell.

14 . The system of claim 11 , wherein:
the shifting operation is determined by the control signal, and wherein the control signal is generated by a Leading Zero Anticipation/Leading Zero Detection unit.

15 . A method comprising:
receiving a first N-bit unsigned number and a second N-bit unsigned number; receiving a control signal indicating a m-bit shifting operation; and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition or subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

16 . The method of claim 15 , wherein the add-and-shift apparatus comprises:
an input block configured to receive a first N-bit unsigned number and a second N-bit unsigned number, wherein the input block comprises N propagate and generate cells; a plurality of calculation cells arranged in rows and columns, wherein the number of the columns is equal to N and the number of the rows is equal to log 2 (N) , wherein each row has N cells and has an index ri, and wherein a variable d is equal to 2 ri , and wherein each calculation cell has three groups of inputs connected to three cells in a preceding row, and wherein:
a first group of inputs are connected to outputs of

Assignees

• Huawei Tech Co Ltd

Inventors

• Ho Huong
• Kafrouni Michel

Classifications

• G06F2207/5063

  2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder · CPC title

• G06F7/506

  with simultaneous carry generation for, or propagation over, two or more stages · CPC title

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/74

  Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders {(with shifting G06F5/01)} · CPC title